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The MMU is implemented as two 16-entry Content Addressable Memory
(CAM). Each entry is referred to as a Cacheability Protection Lookaside
Buffer (CPLB) descriptor. When enabled, every valid entry in the MMU
is examined on any fetch, load, or store operation to determine whether
there is a match between the address being requested and the page
described by the CPLB entry. If a match occurs, the cacheability and pro-
tection attributes contained in the descriptor are used for the memory
transaction with no additional cycles added to the execution of the
instruction.
Because the Level 1 memories are separated into instruction and data
memories, the CPLB entries are also divided between instruction and data
CPLBs. Sixteen CPLB entries are used for instruction fetch requests; these
are called ICPLBs. Another sixteen CPLB entries are used for data transac-
tions; these are called DCPLBs. The ICPLBs and DCPLBs are enabled by
setting the appropriate bits in the Instruction Memory Control
(
IMEM_CONTROL
respectively. These registers are shown in
Figure 6-3 on page
Each CPLB entry consists of a pair of 32-bit values. For instruction
fetches:
•
ICPLB_ADDR[n]
the CPLB descriptor.
•
ICPLB_DATA[n]
CPLB descriptor.
For data operations:
•
DCPLB_ADDR[m]
the CPLB descriptor.
•
DCPLB_DATA[m]
CPLB descriptor.
ADSP-BF535 Blackfin Processor Hardware Reference
) and Data Memory Control (
6-13, respectively.
defines the start address of the page described by
defines the properties of the page described by the
defines the start address of the page described by
defines the properties of the page described by the
) registers,
DMEM_CONTROL
Figure 6-4 on page 6-14
Memory
and
6-57
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