Reset; Spi Flash For Uefi Bios - Kontron CP308 User Manual

Functional Description
Note ...
Care must be taken to ensure that the battery is correctly replaced.
The battery should be replaced only with an identical or equivalent type
recommended by the manufacturer.
Dispose of used batteries according to the manufacturer's instructions.
The typical life expectancy of a 170 mAh battery (CR2025) is 5 - 6 years with
an average on-time of 8 hours per working day at an operating temperature of
30°C. However, this typical value varies considerably because the life
expectancy is dependent on the operating temperature and the standby time
(shutdown time) of the system in which it operates.
To ensure that the lifetime of the battery has not been exceeded, it is recom-
mended to exchange the battery after 4 - 5 years.
2.2.4

Reset

The CP308 is automatically reset by a precision voltage monitoring circuit that detects a drop
in voltage below the acceptable operating limit of 4.7 V for the 5 V line and below 3.1 V for the
3.3 V line, or in the event of a power failure of the DC/DC converters. Other reset sources in-
clude the Watchdog timer and the push-button switch on the 8HP front panel. The CP308 re-
sponds to any of these sources by initializing local peripherals.
A reset will be generated if one the following events occurs:
• +5 V supply falls below 4.7 V typical; level-sensitive
• +3.3 V supply falls below 3.1 V typical; level-sensitive
• Power failure of at least one onboard DC/DC converter; level-sensitive
• Push-button "RESET" pressed (only on CP308-HDD); edge-sensitive
• Watchdog expired; edge-sensitive
• CompactPCI backplane PRST# input (CompactPCI connector J2, pin C17); edge-sensi-
tive
• CompactPCI backplane RST# input (software configurable when the board is in periph-
eral mode); edge-sensitive
• SMC controller generates a reset; configurable to level-sensitive or edge-sensitive (see
Chapter 4.4.1, SMC Controller Status Register 0)
2.2.5

SPI Flash for uEFI BIOS

The CP308 provides two SPI Flash chips for redundant uEFI BIOS. The fail-over mechanism
for the uEFI BIOS recovery can be controlled via the SMC controller or the DIP switch SW1,
switch 1. If one SPI Flash is corrupted, the SMC can enable the second SPI Flash and boot the
system again.
The SPI Flash includes a hardware write protection option, which can be configured via the
uEFI BIOS. If write protection is enabled, the SPI Flash cannot be written to.
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CP308
ID 1027-4487, Rev. 3.0