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Electrical Specifications
Table 2-10. PECI DC Electrical Limits (Sheet 2 of 2)
Symbol
V
p
I
source
I
sink
I
leak+
I
leak-
C
bus
V
noise
Note:
1.
V
supplies the PECI interface. PECI behavior does not affect V
TT
2.
The leakage specification applies to powered devices on the PECI bus.
3.
One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
2.10.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use
Figure 2-1.
Input Device Hysteresis
V
TT
Maximum V
Minimum V
Maximum V
Minimum V
PECI Ground
2.11
Mixing Processors
Intel supports and validates dual processor configurations only in which both
processors operate with the same FSB frequency, core frequency, number of cores, and
have the same internal cache sizes. Mixing components operating at different internal
clock frequencies is not supported and will not be validated by Intel. Combining
processors from different power segments is also not supported.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Definition and Conditions
Positive-edge threshold
voltage
High level output source
(V
= 0.75 * V
OH
Low level output sink
(V
= 0.25 * V
OL
High impedance state
leakage to V
(V
= V
leak
OL
High impedance leakage
to GND
(V
= V
leak
OH
Bus capacitance per node
Signal noise immunity
above 300 MHz
PECI High Range
P
P
N
PECI Low Range
N
Min
0.550 * V
0.725 * V
TT
-6.0
)
TT
0.5
)
TT
N/A
TT
)
N/A
)
N/A
0.1 * V
TT
min/max specifications.
TT
Figure 2-1
as a guide for input buffer design.
Minimum
Hysteresis
1
Max
Units
Notes
V
TT
N/A
mA
1.0
mA
50
µA
2
10
µA
2
10
pF
3
N/A
V
p-p
Valid Input
Signal Range
27
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