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Electrical Specifications
2.10.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use
Figure 2-1.
Input Device Hysteresis
V
TT
Maximum V
Minimum V
Maximum V
Minimum V
PECI Ground
2.11
Mixing Processors
Intel supports and validates dual processor configurations only in which both
processors operate with the same FSB frequency, core frequency, power segments, and
have the same internal cache sizes. Mixing components operating at different internal
clock frequencies is not supported and will not be validated by Intel. Combining
processors from different power segments is also not supported.
Note:
Processors within a system must operate at the same frequency per bits [12:8] of the
CLOCK_FLEX_MAX MSR; however this does not apply to frequency transitions initiated
due to thermal events, Extended HALT, Enhanced Intel SpeedStep
transitions, or assertion of the FORCEPR# signal (See
Not all operating systems can support dual processors with mixed frequencies. Mixing
processors of different steppings but the same model (as per CPUID instruction) is
supported. Details regarding the CPUID instruction are provided in the Intel Processor
Identification and the CPUID Instruction application note.
2.12
Absolute Maximum and Minimum Ratings
Table 2-12
the functional limits of the processor. Only within specified operation limits, can
functionality and long-term reliability be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
®
®
Dual-Core Intel
Xeon
Processor 5100 Series Datasheet
PECI High Range
P
P
N
PECI Low Range
N
specifies absolute maximum and minimum ratings only, which lie outside
Figure 2-1
as a guide for input buffer design.
Minimum
Hysteresis
Chapter
6).
Valid Input
Signal Range
®
Technology
27
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