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Table of Contents
Related Manuals for Intel BX80562QX6700 - Core 2 Extreme 2.66 GHz Processor
Summary of Contents for Intel BX80562QX6700 - Core 2 Extreme 2.66 GHz Processor
- Page 1 Core™2 Extreme Quad-Core Δ Processor QX6000 Sequence and ® Intel Core™2 Quad Processor Δ Q6000 Sequence Datasheet —on 65 nm Process in the 775-land LGA Package supporting ® ® ± Intel 64 architecture and Intel Virtualization Technology August 2007 Document Number: 315592-005...
- Page 2 Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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Page 3: Table Of Contents
Contents Introduction ......................9 Terminology ....................... 9 1.1.1 Processor Terminology ................10 References ....................... 11 Electrical Specifications ................... 13 Power and Ground Lands..................13 Decoupling Guidelines ..................13 2.2.1 VCC Decoupling ..................13 2.2.2 VTT Decoupling ..................13 2.2.3 FSB Decoupling..................14 Voltage Identification .................. - Page 4 7.2.1 Fan Heatsink Power Supply ..............90 Thermal Specifications..................92 7.3.1 Boxed Processor Cooling Requirements............92 ® 7.3.2 Fan Speed Control Operation (Intel Core™2 Extreme processors only) ..94 ® 7.3.3 Fan Speed Control Operation (Intel Core™2 Quad processor) .....94 Debug Tools Specifications ..................97 Logic Analyzer Interface (LAI) ................97...
- Page 5 Figures Static and Transient Tolerance ................20 Overshoot Example Waveform ................21 Differential Clock Waveform ..................29 Differential Clock Crosspoint Specification ..............30 Differential Measurements..................30 Processor Package Assembly Sketch ................31 Processor Package Drawing Sheet 1 of 3 ..............32 Processor Package Drawing Sheet 2 of 3 ..............
- Page 6 Tables References ......................11 Voltage Identification Definition ..................15 Absolute Maximum and Minimum Ratings ..............17 Voltage and Current Specifications................18 Static and Transient Tolerance ................19 Overshoot Specifications..................21 FSB Signal Groups ....................22 Signal Characteristics....................23 Signal Reference Voltages ..................23 GTL+ Signal Group DC Specifications ................24 Open Drain and TAP Output Signal Group DC Specifications ...........24 CMOS Signal Group DC Specifications................25 PECI DC Electrical Limits ...................25...
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Page 7: Revision History
Date Number -001 • Initial release November 2006 ® • Added specifications for the Intel Core™2 Quad Processor Q6600 • Updated Table 8, “Signal Characteristics”. -002 January 2007 • Updated VTT_SEL description in Table 24. • Updated Table 29, “Fan Heatsink Power and Signal Specifications”. - Page 8 Intel architecture enables the processor to execute operating systems and applications written ® to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep technology, allows tradeoffs to be made between performance and power consumption. ® The Core™2 Extreme quad-core processor QX6000 sequence and Intel Core™2 quad processor...
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Page 9: Introduction
Introduction ® ® The Intel Core™2 Extreme quad-core processor QX6000 sequence and Intel Core™2 quad processor Q6000 sequence are the first desktop quad-core processors that combine the performance and power efficiencies of four low-power microarchitecture cores to enable a new level of multi-tasking, multi-media, and gaming experiences. -
Page 10: Processor Terminology
64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http://www.intel.com/technology/intel64/index.htm. -
Page 11: References
VMM, in turn allowing VMMs to be written to common standards and to be more ® ® robust. See the Intel Virtualization Technology Specification for the IA-32 Intel Architecture for more details. References Material and concepts available in the following documents may be beneficial when reading this document. - Page 12 Introduction Datasheet...
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Page 13: Electrical Specifications
Electrical Specifications Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V , while all V lands must be connected to a system ground plane. -
Page 14: Fsb Decoupling
4. Refer to the Intel Core™2 ® Extreme Quad-Core Processor QX6000 Sequence and Intel Core™2 Quad Processor Q6000 Sequence Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, ®... -
Page 15: Voltage Identification Definition
Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 V VID6 VID5 VID4 VID3 VID2 VID1 V CC_MAX CC_MAX 0.8500 1.2375 0.8625 1.2500 0.8750 1.2625 0.8875 1.2750 0.9000 1.2875 0.9125 1.3000 0.9250 1.3125 0.9375 1.3250 0.9500 1.3375 0.9625 1.3500... -
Page 16: Reserved, Unused, And Testhi Signals
Electrical Specifications Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to V , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands. -
Page 17: Voltage And Current Specification
Electrical Specifications Voltage and Current Specification 2.5.1 Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. -
Page 18: Dc Voltage And Current Specification
Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel ®... -
Page 19: V Static And Transient Tolerance
Electrical Specifications specification is based on the V loadline. Refer to for details. Figure 1 CC_MAX CC_MAX 9. These Processors have CPUID = 06FBh The maximum instantaneous current the processor will draw while the thermal control circuit is active (as indicated by the assertion of PROCHOT#) is the same as the maximum I for the processor. -
Page 20: Vcc Static And Transient Tolerance
Electrical Specifications Figure 1. Static and Transient Tolerance Icc [A] VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 Vcc Maximum VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 VID - 0.100 Vcc Typical VID - 0.113 VID - 0.125 VID - 0.138... -
Page 21: Vcc Overshoot
Electrical Specifications 2.5.3 Overshoot The processor can tolerate short transient overshoot events where V exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V is the maximum allowable overshoot voltage). OS_MAX OS_MAX The time duration of the overshoot event must not exceed T... -
Page 22: Signaling Specifications
GTLREF specifications). Termination resistors (R ) for GTL+ signals are provided on the processor silicon and are terminated to V . Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals. -
Page 23: Signal Characteristics
Electrical Specifications Table 7. FSB Signal Groups (Sheet 2 of 2) Signal Group Type Signals A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, CMOS STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#, BSEL[2:], VID[7:0] Open Drain FERR#/PBE#, IERR#, THERMTRIP#, TDO Output Open Drain PROCHOT# Input/Output FSB Clock Clock... -
Page 24: Cmos And Open Drain Signals
Electrical Specifications 2.6.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/ deasserted for at least four BCLKs for the processor to recognize the proper signal state. -
Page 25: Cmos Signal Group Dc Specifications
Electrical Specifications Table 12. CMOS Signal Group DC Specifications Symbol Parameter Unit Notes 2, 3 Input Low Voltage -0.10 * 0.30 3, 4, 5 Input High Voltage * 0.70 + 0.10 Output Low Voltage -0.10 * 0.10 3, 5,6 Output High Voltage 0.90 * V + 0.10 3, 7... -
Page 26: Gtl+ Front Side Bus Specifications
BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Table 15. Core Frequency to FSB Multiplier Configuration... -
Page 27: Fsb Frequency Select Signals (Bsel[2:0])
All agents must operate at the same frequency. ® ® The Intel Core™2 Extreme Quad-Core processor QX6800, QX6700 and Intel Core™2 Quad processors Q6600 and Q6700 operate at a 1066 MHz FSB frequency (selected by ® a 266 MHz BCLK[1:0] frequency). The Intel Core™2 Extreme Quad-Core processor... -
Page 28: Bclk[1:0] Specifications
Electrical Specifications 2.7.4 BCLK[1:0] Specifications Table 17. Front Side Bus Differential BCLK Specifications Symbol Parameter Unit Figure Notes Input Low Voltage -0.30 Input High Voltage 1.15 3, 4, 5 Absolute Crossing Point 0.300 0.550 CROSS(abs) ΔV Range of Crossing Points 0.140 CROSS Overshoot... -
Page 29: Differential Clock Waveform
Electrical Specifications Table 19. FSB Differential Clock Specifications (1333 MHz FSB) T# Parameter Unit Figure Notes 331.635 — 333.364 BCLK[1:0] Frequency 2.99972 — 3.01536 T1: BCLK[1:0] Period 4, 5 — — T2: BCLK[1:0] Period Stability — V/nS T5: BCLK[1:0] Rise and Fall Slew Rate T6: Slew Rate Matching NOTES: Unless otherwise noted, all specifications in this table apply to all processor core frequencies... -
Page 30: Differential Clock Crosspoint Specification
Electrical Specifications Figure 4. Differential Clock Crosspoint Specification 550 mV 550 + 0.5 (VHavg - 700) 300 + 0.5 (VHavg - 700) 300 mV 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 5. -
Page 31: Package Mechanical Specifications
Package Mechanical Specifications Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. -
Page 32: Processor Package Drawing Sheet 1 Of 3
Package Mechanical Specifications Figure 7. Processor Package Drawing Sheet 1 of 3 Datasheet... -
Page 33: Processor Package Drawing Sheet 2 Of 3
Package Mechanical Specifications Figure 8. Processor Package Drawing Sheet 2 of 3 Datasheet... -
Page 34: Processor Package Drawing Sheet 3 Of 3
Package Mechanical Specifications Figure 9. Processor Package Drawing Sheet 3 of 3 Datasheet... -
Page 35: Processor Component Keep-Out Zones
Package Mechanical Specifications Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. -
Page 36: Package Insertion Specifications
This diagram is to aid in the identification of the processor. Figure 10. Processor Top-Side Markings Example for 1066 MHz Processors INTEL ©'05 QX6700 INTEL® CORE™2 EXTREME SLxxx [COO] 2.66GHZ/8M/1066/05B [FPO] ATPO Datasheet... -
Page 37: Processor Top-Side Markings Example For 1333 Mhz Processors
Package Mechanical Specifications Figure 11. Processor Top-Side Markings Example for 1333 MHz Processors INTEL ©'05 QX6850 INTEL® CORE™2 EXTREME SLxxx [COO] 3.00GHZ/8M/1333/05B [FPO] ATPO Datasheet... -
Page 38: Processor Land Coordinates
Package Mechanical Specifications Processor Land Coordinates Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 12. Processor Land Coordinates and Quadrants (Top View) Preliminary Address/ Socket 775 Common Clock/ Quadrants... -
Page 39: Land Listing And Signal Descriptions
Land Listing and Signal Descriptions Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown Figure 13 Figure 14. -
Page 40: Land-Out Diagram (Top View - Left Side)
Land Listing and Signal Descriptions Figure 13. land-out Diagram (Top View – Left Side) FC34 FC31 BSEL1 FC15 FC33 FC32 BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31# RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD D43# D41#... -
Page 41: Land-Out Diagram (Top View - Right Side)
Land Listing and Signal Descriptions Figure 14. land-out Diagram (Top View – Right Side) VID_SEL VSS_MB_ VCC_MB_ VSS_ VCC_ REGULATION REGULATION SENSE SENSE VID7 FC40 VID6 VID2 VID0 VID3 VID1 VID5 VRDSEL PROCHOT# FC25 VID4 ITP_CLK0 FC24 A35# A34# ITP_CLK1 BPM0# BPM1# A33#... - Page 42 Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type Source Synch Input/Output BNR# Common Clock Input/Output Source Synch Input/Output BPM0# Common Clock Input/Output Source Synch Input/Output...
- Page 43 Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type D18# Source Synch Input/Output D57# Source Synch Input/Output D19# Source Synch Input/Output D58# Source Synch...
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Page 44: Alphabetical Land Assignments
Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type FC32 Power/Other RESERVED FC33 Power/Other RESERVED FC34 Power/Other RESERVED FC35 Power/Other RESERVED FC36 Power/Other... - Page 45 Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type TRDY# Common Clock Input AF22 Power/Other TRST# Input Power/Other Power/Other Power/Other Power/Other AG11 Power/Other...
- Page 46 Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type AJ18 Power/Other AM19 Power/Other AJ19 Power/Other AM21 Power/Other AJ21 Power/Other AM22 Power/Other AJ22 Power/Other...
- Page 47 Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
- Page 48 Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type VID_SELECT Power/Other Output Power/Other VID0 Power/Other Output Power/Other VID1 Power/Other Output Power/Other VID2 Power/Other...
- Page 49 Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type AG20 Power/Other AK30 Power/Other AG23 Power/Other Power/Other AG24 Power/Other Power/Other Power/Other AL10 Power/Other Power/Other...
- Page 50 Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
- Page 51 Land Listing and Signal Descriptions Table 23. Alphabetical Land Table 23. Alphabetical Land Assignments Assignments Land Signal Land Signal Land Name Direction Land Name Direction Buffer Type Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VSS_MB_ Power/Other Output...
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Page 52: Numerical Land Assignment
Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other RS2# Common Clock Input D13# Source Synch Input/Output D02# Source Synch Input/Output COMP8 Power/Other... -
Page 53: Vcc
Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type DBI3# Source Synch Input/Output Power/Other D58# Source Synch Input/Output Power/Other Power/Other Power/Other VCCIOPLL Power/Other... - Page 54 Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type D23# Source Synch Input/Output D44# Source Synch Input/Output D24# Source Synch Input/Output D47# Source Synch Input/Output Power/Other...
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Page 55: Vcc
Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type BSEL1 Power/Other Output Power/Other VTT_OUT_LEFT Power/Other Output Power/Other Power/Other Power/Other FC22 Power/Other Power/Other Power/Other... - Page 56 Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other PWRGOOD Power/Other Input Power/Other IGNNE# Asynch CMOS Input Power/Other Power/Other Power/Other RESERVED...
- Page 57 Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other A19# Source Synch Input/Output Power/Other Power/Other MSID1 Power/Other Output Power/Other RESERVED...
- Page 58 Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AB26 Power/Other FC18 Power/Other AB27 Power/Other RESERVED AB28 Power/Other Power/Other AB29 Power/Other RESERVED AB30...
- Page 59 Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AF12 Power/Other AG21 Power/Other AF13 Power/Other AG22 Power/Other AF14 Power/Other AG23 Power/Other AF15 Power/Other...
- Page 60 Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AH30 Power/Other Power/Other BPM1# Common Clock Input/Output AK10 Power/Other BPM0# Common Clock Input/Output AK11 Power/Other ITP_CLK1...
- Page 61 Land Listing and Signal Descriptions Table 24. Numerical Land Table 24. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AL18 Power/Other AM27 Power/Other AL19 Power/Other AM28 Power/Other AL20 Power/Other AM29 Power/Other AL21 Power/Other...
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Page 62: Alphabetical Signals Reference
Land Listing and Signal Descriptions Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 9) Name Type Description A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. - Page 63 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 2 of 9) Name Type Description BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance.
- Page 64 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 3 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64- bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
- Page 65 When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an...
- Page 66 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 5 of 9) Name Type Description Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction HIT# Output snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can HITM# Input/ be continued by reasserting HIT# and HITM# together.
- Page 67 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 6 of 9) Name Type Description LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.
- Page 68 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 7 of 9) Name Type Description RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and RS[2:0]# Input must connect the appropriate pins/lands of all processor FSB agents.
- Page 69 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 8 of 9) Name Type Description In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum T .
- Page 70 Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 9 of 9) Name Type Description This input should be left as a no connect in order for the processor VRDSEL Input to boot. The processor will not boot on legacy platforms where this land is connected to V VSS are the ground pins for the processor and should be connected Input...
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Page 71: Thermal Specifications And Design Considerations
5.1.1 Thermal Specifications To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T... -
Page 72: Processor Thermal Specifications
The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption. -
Page 73: Thermal Profile For 130 W Processors
Thermal Specifications and Design Considerations Table 27. Thermal Profile for 130 W Processors Power Maximum Power Maximum Power Maximum Power Maximum Tc (°C) Tc (°C) Tc (°C) Tc (°C) 42.4 48.2 54.0 59.7 42.7 48.5 54.3 60.1 43.1 48.9 54.6 60.4 43.4 49.2... -
Page 74: Thermal Profile For 105 W Processors
Thermal Specifications and Design Considerations Table 28. Thermal Profile for 105 W Processors Power Maximum Power Maximum Power Maximum Power Maximum Tc (°C) Tc (°C) Tc (°C) Tc (°C) 43.3 48.3 53.4 58.4 43.7 48.7 53.8 58.8 44.0 49.1 54.1 59.1 44.4 49.4... -
Page 75: Thermal Profile 95 W Processors
Thermal Specifications and Design Considerations Table 29. Thermal Profile 95 W Processors Power Maximum Power Maximum Power Maximum Power Maximum Tc (°C) Tc (°C) Tc (°C) Tc (°C) 44.4 52.2 60.1 67.9 45.0 52.8 60.6 68.5 45.5 53.4 61.2 69.0 46.1 53.9 61.8... -
Page 76: Thermal Metrology
26. This temperature specification is meant to help ensure proper operation of the processor. Figure 18 illustrates where Intel recommends T thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). -
Page 77: Thermal Monitor 2
Thermal Specifications and Design Considerations under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a T that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. -
Page 78: On-Demand Mode
Thermal Specifications and Design Considerations Figure 19. Thermal Monitor 2 Frequency and Voltage Ordering Temperature Frequency PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. -
Page 79: Prochot# Signal
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. -
Page 80: Platform Environment Control Interface (Peci)
5.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire; thus, alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. -
Page 81: Peci Specifications
Thermal Specifications and Design Considerations 5.3.2 PECI Specifications 5.3.2.1 PECI Device Address The socket 0 PECI register resides at address 30h and socket 1 resides at 31h. Note that each address also supports two domains (Domain 0 and Domain 1). For more information on PECI domains, refer to the Platform Environment Control Interface Specification. - Page 82 Thermal Specifications and Design Considerations Datasheet...
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Page 83: Features
Features Features Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. -
Page 84: Normal State
LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. Datasheet... -
Page 85: Extended Halt Powerdown State
® ® of the Intel Core™2 Extreme Quad-Core Processor QX6700 and Intel Core™2 Quad Processor Q6000 Sequence Specification Update when available. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state. -
Page 86: Extended Halt Snoop Or Halt Snoop State, Stop Grant Snoop State
Features 6.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. -
Page 87: Boxed Processor Specifications
Boxed Processor Specifications Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor. -
Page 88: Mechanical Specifications
Boxed Processor Specifications Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 22 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. -
Page 89: Space Requirements For The Boxed Processor (Top View)
Boxed Processor Specifications Figure 24. Space Requirements for the Boxed Processor (Top View) NOTES: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 25. Space Requirements for the Boxed Processor (Overall View) Datasheet... -
Page 90: Boxed Processor Fan Heatsink Weight
Boxed Processor Specifications 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. Refer to Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements. 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly... -
Page 91: Boxed Processor Fan Heatsink Power Cable Connector Description
Boxed Processor Specifications Figure 26. Boxed Processor Fan Heatsink Power Cable Connector Description Signal Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. +12 V 0.100" pitch, 0.025" square pin width. SENSE CONTROL Match with straight pin, friction lock header on mainboard. -
Page 92: Thermal Specifications
Boxed Processor Specifications Figure 27. Baseboard Power Header Placement Relative to Processor Socket Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. -
Page 93: Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)
Boxed Processor Specifications Figure 28. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View) Figure 29. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View) Datasheet... -
Page 94: Fan Speed Control Operation (Intel Core™2 Extreme Processors Only)
Boxed Processor Specifications ® 7.3.2 Fan Speed Control Operation (Intel Core™2 Extreme processors only) The boxed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control over fan speed. The fan speed can be controlled by hardware and software from the motherboard. -
Page 95: Boxed Processor Fan Heatsink Set Points
As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage. - Page 96 Boxed Processor Specifications If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet.
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Page 97: Debug Tools Specifications
Debug Tools Specifications Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. - Page 98 Debug Tools Specifications Datasheet...