Table of Contents
Advertisement
4.
The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
Figure 2-8.
Quad-Core Intel® Xeon® Processor X5300 Series VCC Static and Transient
Tolerance Load Lines
V ID - 0 .0 0 0
V ID - 0 .0 2 0
V ID - 0 .0 4 0
V ID - 0 .0 6 0
V ID - 0 .0 8 0
V ID - 0 .1 0 0
V ID - 0 .1 2 0
V ID - 0 .1 4 0
V ID - 0 .1 6 0
V ID - 0 .1 8 0
V ID - 0 .2 0 0
Notes:
1.
The V
CC_MIN
overshoot specifications.
2.
Refer to
3.
Refer to
4.
The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
36
0
5
1 0
1 5
2 0
2 5
3 0
3 5
V
C C
T y p ic a l
and V
loadlines represent static and transient limits. Please see
CC_MAX
Table 2-12
for processor VID information.
Table 2-13
for V
Static and Transient Tolerance
CC
Ic c [A ]
4 0
4 5
5 0
5 5
6 0
6 5
7 0
7 5
V
C C
M in im u m
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Electrical Specifications
8 0
8 5
9 0
9 5
1 0 0 1 0 5 1 1 0 1 1 5 1 2 0 1 2 5
V
C C
M a x im u m
Section 2.13.2
for VCC
Advertisement
Table of Contents
