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Electrical Specifications
Table 2-4.
Loadline Selection Truth Table for LL_ID[1:0]
LL_ID1
0
0
1
1
Note:
The LL_ID[1:0] signals are used by the platform to select the correct loadline slope for the processor.
Table 2-5.
Market Segment Selection Truth Table for MS_ID[1:0]
MS_ID1
0
0
1
1
Note:
The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be
used for future processor compatibility or for keying.
2.6
Reserved, Unused, or Test Signals
All Reserved signals must remain unconnected. Connection of these signals to V
V
, or to any other signal (including each other) can result in component malfunction
SS
or incompatibility with future processors. See
processor and the location of all Reserved signals.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active high inputs, should be connected through a
resistor to ground (V
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. Resistor values should be within ± 20% of the impedance of the baseboard
trace for FSB signals, unless otherwise noticed in the appropriate platform design
guidelines. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (R
Some TAP, CMOS inputs and outputs do not include on-die termination. Inputs and
utilized outputs must be terminated on the baseboard. Unused outputs may be
terminated on the baseboard or left unconnected. Note that leaving unused outputs
unterminated may interfere with some TAP functions, complicate debug probing, and
prevent boundary scan testing. Signal termination for these signal types is discussed in
the appropriate platform design guidelines.
For each processor socket, connect the TESTIN1 and TESTIN2 signals together, then
terminate the net with a 51 Ω resistor to V
Each of the TESTHI signals must be tied to the processor V
matched resistor, where a matched resistor has a resistance value within ± 20% of the
impedance of the board transmission line traces. For example, if the trace impedance is
50 Ω , then a value between 40 Ω and 60 Ω is required.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
LL_ID0
0
Reserved
1
Dual-Core Intel® Xeon® Processor 5000 Series
Dual-Core Intel® Xeon® Processor 5100 Series
0
Reserved
1
Quad-Core Intel® Xeon® Processor 5300 Series
MS_ID0
0
Dual-Core Intel® Xeon® Processor 5000 Series
1
Dual-Core Intel® Xeon® Processor 5100 Series
0
All Quad-Core Intel® Xeon® Processor 5300 Series
1
Reserved
). Unused outputs can be left unconnected; however, this may
SS
TT
Description
Description
Section 4
for a land listing of the
). For details see
Table
TT
.
individually using a
TT
, V
,
CC
TT
2-20.
23
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