Table Of Contents - Intel Quad-Core Xeon Datasheet

Contents
1 Introduction............................................................................................................... 11
1.1 Terminology ..................................................................................................... 13
1.2 State of Data .................................................................................................... 15
1.3 References ....................................................................................................... 15
2 Electrical Specifications ............................................................................................... 17
2.1 Front Side Bus and GTLREF ................................................................................ 17
2.2 Power and Ground Lands.................................................................................... 18
2.3 Decoupling Guidelines ........................................................................................ 18
2.3.1 VCC Decoupling...................................................................................... 18
2.3.2 VTT Decoupling ...................................................................................... 18
2.3.3 Front Side Bus AGTL+ Decoupling ............................................................ 19
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ....................................... 19
2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]) .................................. 20
2.4.2 PLL Power Supply ................................................................................... 21
2.5 Voltage Identification (VID) ................................................................................ 21
2.6 Reserved, Unused, or Test Signals ....................................................................... 23
2.7 Front Side Bus Signal Groups .............................................................................. 24
2.8 CMOS Asynchronous and Open Drain Asynchronous Signals .................................... 26
2.9 Test Access Port (TAP) Connection....................................................................... 26
2.10 Platform Environmental Control Interface (PECI) DC Specifications........................... 26
2.10.1 DC Characteristics .................................................................................. 26
2.10.2 Input Device Hysteresis .......................................................................... 27
2.11 Mixing Processors.............................................................................................. 27
2.12 Absolute Maximum and Minimum Ratings ............................................................. 28
2.13 Processor DC Specifications ................................................................................ 29
2.13.1 Flexible Motherboard Guidelines (FMB) ...................................................... 29
2.13.2 VCC Overshoot Specification .................................................................... 42
2.13.3 Die Voltage Validation ............................................................................. 43
2.14 AGTL+ FSB Specifications................................................................................... 43
3 Mechanical Specifications............................................................................................. 47
3.1 Package Mechanical Drawings ............................................................................. 47
3.2 Processor Component Keepout Zones................................................................... 51
3.3 Package Loading Specifications ........................................................................... 51
3.4 Package Handling Guidelines............................................................................... 52
3.5 Package Insertion Specifications.......................................................................... 52
3.6 Processor Mass Specifications ............................................................................. 52
3.7 Processor Materials............................................................................................ 52
3.8 Processor Markings............................................................................................ 53
3.9 Processor Land Coordinates ................................................................................ 53
4 Land Listing ............................................................................................................... 57
4.1 Quad-Core Intel® Xeon® Processor 5300 Series Pin Assignments ........................... 57
4.1.1 Land Listing by Land Name ...................................................................... 57
4.1.2 Land Listing by Land Number ................................................................... 69
5 Signal Definitions ....................................................................................................... 79
5.1 Signal Definitions .............................................................................................. 79
6 Thermal Specifications ................................................................................................ 87
6.1 Package Thermal Specifications ........................................................................... 87
6.1.1 Thermal Specifications ............................................................................ 87
6.2 ...................................................................................................................... 95
6.2.1 Thermal Metrology ................................................................................. 97
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 3