Electrical Test Circuit; Tck Clock Waveform - Intel Quad-Core Xeon Datasheet

Electrical Specifications
7. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
8. Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
9. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
10. V
Havg
11. For V
IN
12. ΔV
CROSS
Figure 2-13. Electrical Test Circuit
Figure 2-14. TCK Clock Waveform
TCK
T = T55: Period
p
V1, V2: For rise and fall times, TCK is measured between 20% and 80% points on the waveform.
V3: TCK is referenced to 0.5 * V
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
can be measured directly using "Vtop" on Agilent and "High" on Tektronix oscilloscopes.
between 0 V and V .
H
is defined as the total variation of all crossing voltages as defined in Note 3.
TT
V2
V1
T p
V3
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