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Electrical Specifications
Figure 2-11. Quad-Core Intel® Xeon® Processor L5318 V
Load Lines
Notes:
1.
The V
CC_MIN
overshoot specifications.
2.
Refer to
3.
Refer to
4.
The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
Table 2-16. AGTL+ Signal Group Specifications
Symbol
V
IL
V
IH
V
OH
R
ON
I
LI
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
V
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
IL
value.
3.
V
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
IH
value.
4.
V
and V
IH
signal quality specifications.
5.
This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.
Measured at 0.31*V
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
and V
loadlines represent static and transient limits. Please see
CC_MAX
Table 2-12
for processor VID information.
Table 2-15
for V
Static and Transient Tolerance.
CC
Parameter
Input Low Voltage
Input High Voltage
GTLREF+0.10
Output High Voltage
Buffer On Resistance
Input Leakage Current
may experience excursions above V
OH
. R
(min) = 0.225*R
TT
ON
Static and Transient Tolerance
CC
Min
Typ
-0.10
0
GTLREF-0.10
V
TT
V
- 0.10
N/A
TT
10.00
11.50
N/A
N/A
. However, input signal drivers must comply with the
TT
. R
(typ) = 0.250*R
TT
ON
Section 2.13.2
Max
Units
Notes
V
V
+0.10
V
TT
V
V
TT
13.00
Ω
± 200
μA
. R
(max) = 0.275*R
.
TT
ON
TT
for VCC
1
2,4,6
3,6
4,6
5
7,8
41
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