Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual page 99

Table 10-16: MAC Header Filter Configuration Registers (Cont'd)
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Address Default
PLB_base_address 0x00000000
+ 0x3000
+ (filter# * 0x20)
+ 0xC
PLB_base_address 0xFFFFFFFF
+ 0x3000
+ (filter# * 0x20)
+ 0x10
PLB_base_address 0x0000FFFF
+ 0x3000
+ (filter# * 0x20)
+ 0x14
PLB_base_address 0x00000000
+ 0x3000
+ (filter# * 0x20)
+ 0x18
PLB_base_address 0x00000000
+ 0x3000
+ (filter# * 0x20)
+ 0x1C
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PLB Address Map and Register Definitions
Access
R/W Match Pattern: Ethernet frame bits 96 to 127
32 bit pattern to match against the Ethernet
frame bits 96 to 127.
For frames with a VLAN tag, match pattern
bits[31:0] can be matched against the full
VLAN field.
For frames without a VLAN, match pattern
bits[15:0] can be matched against the
Length/Type field.
R/W Match Enable: Ethernet frame bits 0 to 31
There is a 1-to-1 correspondence between all
bits in this register and all bits in the "Match
Pattern: Ethernet frame bits 0 to 31" register.
For each bit:
logic 1 enables the match: the corresponding
bit in the Match Pattern will be compared
logic 0 disables the match: the corresponding
bit in the Match Pattern will be a don't-care.
R/W Match Enable: Ethernet frame bits 32 to 63
There is a 1-to-1 correspondence between all
bits in this register and all bits in the "Match
Pattern: Ethernet frame bits 32 to 63" register.
For each bit:
logic 1 enables the match: the corresponding
bit in the Match Pattern will be compared
logic 0 disables the match: the corresponding
bit in the Match Pattern will be a don't-care.
R/W Match Enable: Ethernet frame bits 64 to 95
There is a 1-to-1 correspondence between all
bits in this register and all bits in the "Match
Pattern: Ethernet frame bits 64 to 95" register.
For each bit:
logic 1 enables the match: the corresponding
bit in the Match Pattern will be compared
logic 0 disables the match: the corresponding
bit in the Match Pattern will be a don't-care.
R/W Match Enable: Ethernet frame bits 96 to 127
There is a 1-to-1 correspondence between all
bits in this register and all bits in the "Match
Pattern: Ethernet frame bits 96 to 127" register.
For each bit:
logic 1 enables the match: the corresponding
bit in the Match Pattern will be compared
logic 0 disables the match: the corresponding
bit in the Match Pattern will be a don't-care.
Description
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