Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual page 21

Acronym
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Spelled Out
PHY physical-side interface
PHYAD Physical Address
PLB Processor Local Bus
PTP Precise Timing Protocol
REGAD Register Address
RTC Real Time Clock
RO Read Only
R/W Read/Write
Rx Receive
SFD Start of Frame Delimiter
SRP Stream Reservation Protocol
TEMAC Tri-Mode Ethernet MAC
TCP/IP Transmission Control Protocol / Internet Protocol.
TOE TCP/IP Offload Engine
Tx Transmitter
UCF User Constraints File
us microseconds
VHDL VHSIC Hardware Description Language
(VHSIC an acronym for Very High-Speed Integrated Circuits)
VLAN Virtual LAN (Local Area Network)
WO Write Only
XCO Xilinx CORE Generator core source file
XPS Xilinx Platform Studio (part of the EDK software)
XPS_LL_TEMAC XPS LocalLink Tri-Mode Ethernet MAC
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Conventions
21