Conventions; Typographical - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

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Preface: About This Guide

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:
18
Chapter 13, "Software Drivers"
delivered with the core.
Chapter 14, "Quick Start Example Design"Chapter 14, "Quick Start Example Design,"
provides instructions to quickly generate the core and run the example design
through implementation and simulation using the default settings.
Chapter 15, "Detailed Example Design (Standard Format)"
information about the core when generated in the standard CORE Generator format,
including a description of files and the directory structure generated
Chapter 16, "Detailed Example Design (EDK format)"
about the core when generated in the Standard Embedded Development Kit (EDK)
format, including a description of files and the directory structure generated.
Appendix A, "RTC Time Stamp Accuracy"
stamps, essential to the Precise Timing Protocol across the network link, and provides
some of the ways inaccuracies are introduced.
Convention
Messages, prompts, and
program files that the system
Courier font
displays. Signal names in text
also.
Literal commands that you enter
Courier bold
in a syntactical statement
Commands that you select from
a menu
Helvetica bold
Keyboard shortcuts
Variables in a syntax statement
for which you must supply
values
Italic font
References to other manuals
Emphasis in text
Items that are not supported or
Dark Shading
reserved
An optional entry or parameter.
However, in bus specifications,
Square brackets [ ]
such as bus[7:0], they are
required.
www.xilinx.com
describes the function of the software drivers
describe the necessity of accurate time
Meaning or Use
Ethernet AVB Endpoint User Guide
provides detailed
provides detailed information
Example
speed grade: - 100
ngdbuild design_name
File → Open
Ctrl+C
ngdbuild design_name
See the User Guide for more
information.
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
This feature is not supported
ngdbuild [option_name]
design_name
UG492 September 21, 2010

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