Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Software
  5. LogiCORE Endpoint v2.4
  6. User manual
Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
TM
LogiCORE
IP
Ethernet AVB
Endpoint v2.4
User Guide
UG492 September 21, 2010

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the LogiCORE IP Ethernet AVB Endpoint v2.4 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4

Summary of Contents for Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4

  • Page 1 LogiCORE Ethernet AVB Endpoint v2.4 User Guide UG492 September 21, 2010...

  • Page 2: Revision History

    Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information.

  • Page 3: Table Of Contents

    ........... . . 32 Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 4 Errored AV Traffic Reception..........74 www.xilinx.com...
  • Page 5 Timing Constraints ............103 Chapter 12: System Integration Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs ....111 LogiCORE IP Tri-Mode Ethernet MAC (Soft Core) .
  • Page 6 Customizing the Test Bench ..........157 www.xilinx.com...
  • Page 7 Accuracy Resulting from the Combined Errors ......171 Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 8 Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 9: Schedule Of Figures

    Figure 8-3: Time Stamping Position ..........80 Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 10 Figure 15-3: Simulator Wave Window Contents ....... . . 158 www.xilinx.com...
  • Page 11 Figure A-4: Overall Time Stamp Accuracy ........171 Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 12 Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 13: Schedule Of Tables

    Table 10-5: Tx Arbiter Idle Slope Control Register (PLB_base_address + 0x2010) ..94 Table 10-6: RTC Nanoseconds Field Offset (PLB_base_address + 0x2800) ... . 94 Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 14 Table 16-6: pcore netlist Directory..........162 www.xilinx.com...
  • Page 15 Table 16-9: Driver Source Directory ..........164 Appendix A: RTC Time Stamp Accuracy Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 16 Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 17: Preface: About This Guide

    Ethernet AVB core constraints. • Chapter 12, “System Integration” describes the integration of the Ethernet AVB Endpoint core into a system, including connection of the core to the Xilinx Tri-Mode Ethernet MAC and Ethernet Statistic cores. Ethernet AVB Endpoint User Guide www.xilinx.com...

  • Page 18: Conventions

    Dark Shading This feature is not supported reserved An optional entry or parameter. However, in bus specifications, ngdbuild [option_name] Square brackets [ ] such as bus[7:0], they are design_name required. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 19: Online Document

    Cross-reference link to a Figure 2-5 in the Virtex-5 Red text location in another document FPGA User Guide. Go to www.xilinx.com for the Blue, underlined text Hyperlink to a website (URL) latest speed files. Ethernet AVB Endpoint User Guide www.xilinx.com...

  • Page 20: List Of Abbreviations

    Megabits per second MDIO Management Data Input/Output Microprocessor Hardware Description: a proprietary file format, using the .mhs file extension, for a XPS project Mega Hertz milliseconds MPMC Multi-Port Memory Controller nanoseconds www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 21 (VHSIC an acronym for Very High-Speed Integrated Circuits) VLAN Virtual LAN (Local Area Network) Write Only Xilinx CORE Generator core source file Xilinx Platform Studio (part of the EDK software) XPS_LL_TEMAC XPS LocalLink Tri-Mode Ethernet MAC Ethernet AVB Endpoint User Guide www.xilinx.com...
  • Page 22 Preface: About This Guide www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 23: Chapter 1: Introduction

    ISE® software v12.2 About the Core The Ethernet AVB Endpoint core is available through the Xilinx CORE Generator™ software included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see the Ethernet AVB Endpoint product page.

  • Page 24: Recommended Design Experience

    For technical support, see www.support.xilinx.com/. Questions are routed to a team of engineers with expertise using the Ethernet AVB Endpoint core. Xilinx provides technical support for use of this product as described in this guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines.

  • Page 25: Document

    Feedback Document For comments or suggestions about this document, submit a WebCase from www.xilinx.com/support/clearexpress/websupport.htm/ Be sure to include the following information: • Document title • Document number • Page number(s) to which your comments refer • Explanation of your comments Ethernet AVB Endpoint User Guide www.xilinx.com...
  • Page 26 Chapter 1: Introduction www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 27: Chapter 2: Licensing The Core

    Xilinx Core Site License Agreement. Before you Begin This chapter assumes that you have installed the required Xilinx® ISE® Design Suite version following the instructions provided by the Xilinx ISE Installation, Licensing and Release Notes Guide, www.xilinx.com/support/documentation/dt_ise.htm. Detailed software requirements can be found on the product web page for this core, www.xilinx.com/products/ipcenter/DO-DI-EAVB-EPT.htm.

  • Page 28: Full

    Click Evaluate. Follow the instructions to install the required Xilinx ISE software and IP Service Packs. Obtaining a Full License Key To obtain a Full license key, please follow these instructions: Purchase the license through your local sales office. Once the order has been entered, an email will be sent to your Account Administrator with instructions on how to access the account.

  • Page 29: Chapter 3: Overview Of Ethernet Audio Video Bridging

    X-Ref Target - Figure 3-1 Home Network (wireless) Terrestrial Broadcast Home Network Home Network (wired) Satellite DVD player Broadband Figure 3-1: Example AVB Home Network Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 30: Avb Specifications

    The hardware components are incorporated into the core, and the software component is provided with the core in the form of drivers. These drivers should be run on an embedded processor (MicroBlaze™ or PowerPC®). www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 31: P802.1Qav

    AV traffic Ethernet frames. Buffering is expected to be done outside the Ethernet AVB Endpoint, after it has separated out the AV traffic Ethernet frames, as the buffering requirements are expected to be application-specific. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 32: P802.1Qat

    3-1, as opposed to an intermediate bridge function, which is not supported. In the implementation, the Ethernet AVB Endpoint core is shown connected to a Xilinx Tri- Mode Ethernet MAC core, which in turn is connected to an AVB capable network. All devices attached to this network should be AVB capable to obtain the full Quality of Service advantages for the AV traffic.
  • Page 33 The IEEE1722 is also an evolving standard which will specify the embedding of audio/video data streams into Ethernet Packets. The 1722 headers within these packets can optionally include presentation time stamp information. Contact Xilinx for further system-level information. Ethernet AVB Endpoint User Guide www.xilinx.com...
  • Page 34 Chapter 3: Overview of Ethernet Audio Video Bridging www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 35: Ethernet Avb Gui

    Graphical User Interface (GUI) for defining parameters and options. For help starting and using the CORE Generator software, see the documentation supplied with the ISE® software, including the CORE Generator User Guide, available from www.xilinx.com/support/software_manuals.htm. Ethernet AVB GUI Page 1 Figure 4-1 shows page 1 of the Ethernet AVB Endpoint GUI customization screen.

  • Page 36: Chapter 4: Generating The Core

    When generated in this format, page 2 of the GUI is not available; the “PLB Interface” will be configured dynamically by the EDK Xilinx Platform Studio (XPS) software. For directory and file definitions for the two available formats, see Chapter 15, “Detailed Example Design (Standard Format)”...

  • Page 37: Ethernet Avb Gui

    Valid range is 0x00000000 to 0xFFFF8000. The least significant 15 bits of the base address must be set to 0 (bits 17 to 31 of the PLB Base Address). Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 38: Parameter Values In The Xco File

    HDL example design. • Chapter 14, “Quick Start Example Design” • Chapter 15, “Detailed Example Design (Standard Format)” • Chapter 16, “Detailed Example Design (EDK format)” www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 39: Chapter 5: Core Architecture

    Format”(provided for the Embedded Development Kit) This option will deliver the core in the standard pcore format, suitable for directly importing into the Xilinx Embedded Development Kit (EDK) environment. When generated in this format, the core is designed to interface to the XPS LocalLink Tri-Mode Ethernet MAC (xps_ll_temac).

  • Page 40: Standard Core Generator Format

    Rx Time Stamp Host I/F Legacy Traffic Legacy Traffic I/F Rx Splitter MAC Header Filters Figure 5-1: Ethernet AVB Endpoint Core Block Diagram for Connection to LogiCORE IP Tri-Mode Ethernet www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 41: Edk Pcore Format

    Rx PHY Legacy Traffic Legacy Traffic I/F Rx Splitter Avb2TemacRxData Temac2AvbTxData Figure 5-2: Ethernet AVB Endpoint Core Block Diagram for Connection to the XPS Tri-Mode Ethernet MAC (xps_ll_temac) in the EDK Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 42: Functional Block Description

    “Standard CORE Generator Format”, the PLB logic provides a logic shim which is connected to the Host I/F of the supported Xilinx Tri- Mode MAC core; this enables all configuration and status registers of the MAC to also be available via the PLB. See Chapter 10, “Configuration and Status”...

  • Page 43: Tx Arbiter

    Chapter 7, “Ethernet AVB Endpoint Reception” further information. When the core is generated in “EDK pcore Format”, the “Legacy MAC Header Filters” not included since the xps_ll_temac can optionally contain its own Address Filter logic. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 44: Precise Timing Protocol Blocks

    Rx PTP buffer raises its dedicated interrupt, this time stamp is available for the microprocessor to read. This sampling of the RTC is performed in hardware for accuracy. Chapter 9, “Precise Timing Protocol Packet Buffers” for further information. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 45 RTC increment rate. Xilinx recommends clocking the RTC logic at 125 MHz because this is a readily available clock source (obtained from the transmit clock source of the Ethernet MAC at 1 Gbps speed).

  • Page 46: Software Drivers

    Chapter 13, “Software Drivers” for further information. Tri-Mode Ethernet MACs Although not part of the Ethernet AVB Endpoint core, a Xilinx Tri-Mode Ethernet MAC core is a requirement of the system (see Figure 5-1 Figure 5-2). The IEEE Audio Video Bridging technology stipulates the following configuration requirements on this MAC: •...

  • Page 47: Core Interfaces

    Input Asynchronous reset for the entire core rtc_clk Input Reference clock used to increment the “RTC.” minimum frequency is 25 MHz. Xilinx recommends a 125 MHz clock source. tx_clk Input The MAC transmitter clock, provided by the Tri-Mode Ethernet MAC.

  • Page 48: Legacy Traffic Interface

    Resets”). Table 5-3: Legacy Traffic Signals: Receiver Path Signal Direction Description legacy_rx_data[7:0] Output Legacy frame data received is supplied on this port. legacy_rx_data_valid Output Control signal for the legacy_rx_data[7:0] port www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 49: Av Traffic Interface

    Asserted by the AV client to indicate that further frames, following the current frame, are/are not held in a queue. av_tx_ack Output Handshaking signal asserted when the current data on av_tx_data[7:0] has been accepted. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 50: Tri-Mode Ethernet Mac Client Interface

    Output Asserted to force the MAC to corrupt the current frame tx_ack Input Handshaking signal asserted when the current data on tx_data[7:0] has been accepted by the MAC. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 51 Output When asserted, the MAC will access the MDIO port, when not asserted, the MAC will access configuration registers host_req Output Used to initiate a transaction onto the MDIO Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 52: Processor Local Bus (Plb) Interface

    Processor Local Bus (PLB) Interface The Processor Local Bus (PLB) on the Ethernet Audio Video core is designed to be integrated directly in the Xilinx Embedded Development Kit (EDK) where it can be easily integrated and connected to the supported embedded processors (MicroBlaze or PowerPC).
  • Page 53 PLB read burst transfer indicator. PLB_rdPendReq Input Unused. PLB pending read request priority. PLB_wrPendReq Input Unused. PLB pending write request priority. PLB_rdPendPri[0:1] Input Unused. PLB pending read bus request indicator. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 54 Unused, tied to logic 0. Slave write error indicator. Sl_MRdErr[0:NUM_MASTERS-1] Output Unused, tied to logic 0. Slave read error indicator. Sl_MIRQ[0:NUM_MASTERS-1] Output Unused, tied to logic 0. Slave interrupt indicator. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 55: Interrupt Signals

    This is asserted following the transmission of any PTP packet from the “Tx PTP Packet Buffers.” interrupt_ptp_rx Output This is asserted following the reception of any PTP packet into the “Rx PTP Packet Buffers.” Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 56: Ptp Signals

    IEEE802.1 AS RTC. If desired, this port can be used as the RTC reference for 1722 Packet Manager blocks, Figure 3-2 as illustrated in . See also “IEEE1722 Real Time Clock Format,” page www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 57: Chapter 6: Ethernet Avb Endpoint Transmission

    5-1). This interface is intentionally identical to the client transmitter interface of the supported Xilinx Tri-Mode Ethernet MAC core (there is a one-to-one correspondence between signal names of the block-level wrapper from the Tri-Mode Ethernet MAC example design, after the legacy_ prefix is removed). This provides backwards compatibility–all existing MAC client-side designs can connect to the legacy Ethernet port unmodified.

  • Page 58: Error Free Legacy Frame Transmission

    The end of frame is signalled to the core by taking the legacy_tx_data_valid to logic 0. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 59: Errored Legacy Frame Transmission

    Additionally, the AV does not contain a signal that is equivalent to legacy_tx_underrun: no mechanism is currently provided on the AV interface to signal an error in a frame which is currently undergoing transmission. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 60 This helps achieve in excess of the 25% minimum allocation for the legacy traffic. However, holding off the assertion of av_tx_done will not act as cheat mode to exceed the maximum bandwidth allocation for the AV traffic. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 61: Tx Arbiter

    To enforce the bandwidth policing of the AV Traffic, a credit-based shaper algorithm has been implemented in the Ethernet AVB Endpoint core. Figure 6-4 illustrates the basic operation of the algorithm and indicates how the Tx Arbiter decides which Ethernet frame to transmit. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 62 When AV traffic is queued, and until the time at which the Tx Arbiter is able to schedule it (while waiting for an in-progress legacy frame to complete transmission), credit can be gained at a rate defined by the idleSlope. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 63 The calculated value for the sendSlopeValue should be written directly to the “Tx Arbiter Send Slope Control Register.” This provides a per-byte decrement value when relating this to AV Ethernet frame transmission. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 64 AV frames. In this example, dedicating up to 75% of the total bandwidth to the AV traffic, we obtain: loLimitValue = 1518 x 2048 = 3108864 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 65: Chapter 7: Ethernet Avb Endpoint Reception

    Table 5-1). This interface is intentionally identical to the client receiver interface of the supported Xilinx Tri-Mode Ethernet MAC core (there is a one-to-one correspondence between signal names of the block-level wrapper from the Tri-Mode Ethernet MAC example design, after the legacy_ prefix is removed).

  • Page 66: Error Free Legacy Frame Reception

    The core asserts the legacy_rx_frame_good signal to indicate that the frame was intended for the legacy traffic client and was successfully received without error. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 67: Errored Legacy Frame Reception

    Destination Address, Length/Type Field, VLAN tag (if present), or any bit-wise match combination of the preceding. Eight individual MAC Header Filters are provided, numbered from 0 through to 7, each of which is separately configured. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 68 Frame Destination Address (DA) contained a Broadcast Address. • Every bit within the legacy_rx_filter_match[7:0] bus will be asserted when the MAC Header Filter is operating in Promiscuous Mode (see “Rx Filtering Control Register”). www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 69 The overall result of the Match Pattern Register and Match Enable Register is to provide a highly configurable and flexible MAC Header matching logic as the “Single MAC Header Filter Usage Examples” demonstrates. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 70 48-bits of the received frame must exactly match the first 48-bits of the Match Pattern Register. This example provides backwards compatibility with the Address Filters provided in the Tri-Mode Ethernet MAC (which must be disabled). www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 71 29-bits (as used in this example) of the received frame must exactly match the first 29-bits of the Match Pattern Register. This functionality is useful for filtering across Multicast group Addresses. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 72 128-bits of an Ethernet frame, match combinations of Destination Address, Length/Type Field (when no VLAN tag is present), VLAN fields (when present) can be selected with complete flexibility. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 73: Rx Av Traffic I/F

    AV receive client until the frame is complete. The core asserts the av_rx_frame_good to indicate that the frame was intended for the AV traffic client, and was successfully received without error. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 74: Errored Av Traffic Reception

    (in place of av_rx_frame_good) indicates that this frame must be discarded by the AV client; it was either received with errors or was not intended for the AV traffic interface. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 75: Chapter 8: Real Time Clock And Time Stamping

    Nano Seconds field (32 bits unsigned) counts from 0 until fully saturated, counts from 0 to 1 x 10 then wraps around to 0 then resets to 0 Figure 8-1: Real Time Counter (RTC) Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 76 RTC increment rate. Xilinx recommends clocking the RTC logic at 125 MHz because this is a readily available clock source (obtained from the transmit clock source of the Ethernet MAC at 1 Gbps speed): this frequency will significantly exceed the minimum performance of the P802.1AS specification.

  • Page 77: Rtc Implementation

    RTC Increment Value (26 bits) (written by processor) controlled frequency RTC Step 2 RTC Nano Seconds Offset (30 bits) (written by processor) Synchronised RTC Figure 8-2: Increment of Sub-nanoseconds and Nanoseconds Field Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 78 Again, the step correction capability can be used to either initialize the RTC counter following reset, or to synchronize the local RTC to that of the Grand Master Clock (when the local device is acting as a clock slave). www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 79: Clock Outputs Based On The Synchronized Rtc Nanoseconds Field

    “RTC Offset Control Registers” (effectively performing the step 2 calculation of Figure 8-2 software). Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 80: Time Stamp Sampling Position Of Mac Frames

    1000BASE-X or SGMII physical interface, the GMII exists only as an internal connection within the embedded block. Therefore, by sampling on the client interface, we enable the Ethernet AVB Endpoint core to be connected to ANY Xilinx Tri-Mode MAC used in ANY configuration.

  • Page 81: Ieee1722 Real Time Clock Format

    IEEE1722 Real Time Clock Format Because the Xilinx Tri-Mode Ethernet MACs have a known fixed latency, the time stamps taken can easily be translated into the equivalent GMII position to comply with the standard. This is performed in the software drivers where the MAC transmitter and receiver latencies are held in #defines in a header file.
  • Page 82 Chapter 8: Real Time Clock and Time Stamping www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 83: Chapter 9: Precise Timing Protocol Packet Buffers

    “Real Time Clock”. Following the end of PTP frame transmission, this captured timestamp will automatically be written into this location to accompany the frame for which it was taken. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 84 Frame 0x1400 Pdelay_Resp Frame PTP Frame Data 0x1300 Pdelay_Req Frame 0x1200 0x08 reserved Follow_Up Frame frame_length_field 0x00 0x1100 Sync Frame byte-wide data 0x1000 Figure 9-1: Tx PTP Packet Buffer Structure www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 85 “Rx PTP Packet Control Register” will indicate the most recently filled Buffer Number. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 86: Figure 9-2: Rx Ptp Packet Buffer

    0xFD timestamp[7:0] 0xFC 0x0B00 0x0A00 unused frame size 0x0900 0x0800 0x0700 0x0600 PTP Frame Data 0x0500 0x0400 0x0300 0x00 0x0200 0x0100 byte-wide data 0x0000 Figure 9-2: Rx PTP Packet Buffer www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 87: Chapter 10: Configuration And Status

    The Processor Local Bus (PLB) bus on the Ethernet AVB Endpoint core is designed to be integrated directly in the Xilinx Embedded Development Kit (EDK) where it can be easily integrated and connected to the supported embedded processors (MicroBlaze™ or PowerPC®).

  • Page 88: Figure 10-1: Single Read Transaction

    PLB_RNW 11111111 PLB_BE[0:7] 0000 PLB_size[0:3] PLB_type[0:2] PLB_abort PLB_ABus[0:31] PLB_PAValid SI_wait SI_addrAck PLB_wrDBus[0:31] SI_wrDAck SI_wrComp PLB_wrBurst SI_rdDBus[0:31] 0000 D(A0) 0000 SI_rdWrAddr[0:3] 0000 0000 SI_rdDAck SI_rdComp PLB_rdBurst Figure 10-1: Single Read Transaction www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 89: Single Write Transaction

    X-Ref Target - Figure 10-2 PLB_clk PLB_RNW PLB_BE[0:7] 11111111 PLB_size[0:3] 0000 PLB_type[0:2] PLB_abort PLB_ABus[0:31] PLB_AValid SI_wait SI_addrAck PLB_wrDBus[0:31] D(A0) SI_wrDAck SI_wrComp PLB_wrBurst 0000 SI_rdDBus[0:31] 0000 SI_rdWrAddr[0:3] SI_rdDAck SI_rdComp PLB_rdBurst Figure 10-2: Single Write Transaction Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 90: Plb Address Map And Register Definitions

    “PLB Base Address” in Chapter 4) when the core is generated in “Standard CORE Generator Format”. • automatically assigned and configured when the core is generated in “EDK pcore Format”. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 91 0x2000 Reserved 0x1800 Tx PTP Packet Buffer 0x1000 RxPTP Packet Buffer PLB_base_address + 0x0000 Figure 10-3: PLB Address Space of the Ethernet AVB Endpoint Core and Connected Tri-Mode Ethernet MAC Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 92: Ethernet Avb Endpoint Address Space

    (block RAM bin position) of the most recently transmitted PTP packet. 31-19 Unused Note: A read or a write to this register clears the interrupt_ptp_tx interrupt (asserted after each successful PTP packet transmission). www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 93 All frames will be passed to the “Rx Legacy Traffic I/F.” If set to 0 then only matching MAC headers are passed to the “Rx Legacy Traffic I/F.” Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 94 When in PTP clock slave mode, the “Software Drivers” use this register to implement the periodic step corrections. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 95 Current RTC Value Registers Table 10-10 describes the nanoseconds field value register for the nanoseconds field of the “Real Time Clock.” When read, this will return the latest value of the counter. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 96 PLB_base_address Bit no Default Access Description Write ANY value to bit 0 of this register to clear the interrupt_ptp_timer Interrupt signal. This bit always returns 0 on read. 31-1 Unused www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 97 PTP transmitter logic of the core to be reset. This is a subset of the full transmitter path reset of bit This reset does not affect PTP transmitter configuration settings. If read, always returns 0. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 98 + 0x3000 32 bit pattern to match against the Ethernet frame bits 64 to 95. Specifically, match pattern + (filter# * 0x20) bits: + 0x8 [31:0]: MAC Source Address bits [47:16] www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 99 1 enables the match: the corresponding bit in the Match Pattern will be compared logic 0 disables the match: the corresponding bit in the Match Pattern will be a don’t-care. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 100: Tri-Mode Ethernet Mac Address Space

    MAC Header Filters” have been added to the Receiver Legacy Traffic path, which is capable of providing address recognition for eight unique MAC addresses. See “MAC Header Filter Configuration.” www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 101 MDIO_ADDRESS is a 10-bit binary address, constructed from the 5-bit MDIO Physical Address (PHYAD) and the 5-bit MDIO Register Address (REGAD) as follows: MDIO_ADDRESS <= {PHYAD, REGAD} See the Tri-Mode Ethernet MAC User Guide and IEEE802.3 for further MDIO information. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 102 Chapter 10: Configuration and Status www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 103: Chapter 11: Constraining The Core

    These clock nets and the signals within the core that cross these clock domains must be constrained appropriately in a UCF. Sections of UCF syntax are used in the following descriptions to provide examples. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 104 The following UCF syntax shows the necessary constraints being applied to rx_clk: NET "rx_clk" TNM_NET = "rx_clk"; TIMEGRP "rx_clock" = "rx_clk"; TIMESPEC "TS_rx_clock" = PERIOD "rx_clock" 8000 ps HIGH 50 %; www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 105 RTC increment rate. Xilinx recommends clocking the RTC logic at 125 MHz because this is a readily available clock source (obtained from the transmit clock source of the Ethernet MAC at 1 Gbps speed).
  • Page 106 # clock domain crossing constraints for Rx Configuration #--------------------------------------------------------- INST "*top/avb_configuration_inst/promiscuous_mode_int" TNM = FFS "promiscuous_mode"; INST "*top/legacy_inst*address_filter_inst/*resync_promiscuous_mode/data_sy nc" TNM = FFS "promiscuous_mode_resync"; TIMESPEC "ts_promiscuous_mode" = FROM "promiscuous_mode" TO "promiscuous_mode_resync" TIG; www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 107 "resync_cpu_tx_wr_toggle" TIG; INST "*top/avb_configuration_inst/tx_cpu_reclock/new_be*" TNM = FFS "tx_cpu_sample"; INST "*top/avb_configuration_inst/tx_cpu_reclock/new_addr*" TNM = FFS "tx_cpu_sample"; TIMESPEC "ts_tx_cpu_sample" = FROM "cpu_bus" TO "tx_cpu_sample" 16 ns DATAPATHONLY; INST "*top/avb_configuration_inst/clear_tx_int" TNM = FFS "tx_regs_sample"; Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 108 TIMESPEC "ts_cpu_rtc_wr_toggle" = FROM "cpu_rtc_wr_toggle" TO "resync_cpu_rtc_wr_toggle" TIG; INST "*top/rtc_inst/rtc_configuration_inst/rtc_cpu_reclock/new_be*" TNM = FFS "rtc_cpu_sample"; INST "*top/rtc_inst/rtc_configuration_inst/rtc_cpu_reclock/new_addr*" TNM = FFS "rtc_cpu_sample"; TIMESPEC "ts_rtc_cpu_sample" = FROM "cpu_bus" TO "rtc_cpu_sample" 16 ns DATAPATHONLY; www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 109 INST "*top*generic_host_if_inst/host_address*" TNM = FFS "host_sample"; INST "*top*generic_host_if_inst/stats_upper_word*" TNM = FFS "host_sample"; INST "*top*generic_host_if_inst/host_wr_data*" TNM = FFS "host_sample"; INST "*top*generic_host_if_inst/host_be*" TNM = FFS "host_sample"; TIMESPEC "ts_host_sample" = FROM "cpu_bus" TO "host_sample" 8 ns DATAPATHONLY; Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 110 TIMESPEC "ts_host_toggle" = FROM "host_toggle" TO "resync_host_toggle" 8 ns DATAPATHONLY; INST "*top*generic_host_if_inst/host_rd_data_result*" TNM = FFS "host_rd_data"; INST "*top*generic_host_if_inst/cpu_rd_data*" TNM = FFS "cpu_rd_data"; TIMESPEC "ts_cpu_rd_data" = FROM "host_rd_data" TO "cpu_rd_data" 8 ns DATAPATHONLY; www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 111: Chapter 12: System Integration

    “EDK pcore Format” This option will deliver the core in the standard pcore format, suitable for directly importing into the Xilinx Embedded Development Kit (EDK) environment. When generated in this format, the core is designed to interface to the XPS LocalLink Tri-Mode Ethernet MAC (xps_ll_temac).

  • Page 112: Logicore Ip Tri-Mode Ethernet Mac (Soft Core)

    • Management Interface. Enabled • Clock Enables. Enabled • Address Filter. Disabled See the Tri-Mode Ethernet MAC User Guide (UG138) for additional information. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 113 Figure 12-1: Connection to the Tri-Mode Ethernet MAC Core (without Ethernet Statistics) Figure 12-1 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri- Mode Ethernet MAC (TEMAC) core when not using the Ethernet Statistics core. Figure 12-1...
  • Page 114 The host_clk inputs of the Ethernet AVB Endpoint and of the TEMAC must always share the same clock source. If desired, this can also be the clock source used for the PLB interface. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 115: Mac Management

    Figure 12-2: Connection to the Tri-Mode Ethernet MAC and Ethernet Statistic Cores Figure 12-2 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri- Mode Ethernet MAC (TEMAC) core when using the Ethernet Statistics core. This shares...

  • Page 116: Logicore Ip Embedded Tri-Mode Ethernet Macs

    • EMAC0 Configuration. Enable VLAN Enable in both the Transmitter Configuration and Receiver Configuration boxes See the Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide (UG340) for additional information. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 117: Without Ethernet Statistics

    Figure 12-3: Connection to the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC (without Ethernet Statistics) Figure 12-3 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri- Mode Ethernet MAC (EMAC) core when not using the Ethernet Statistics core. Figure 12-3...
  • Page 118 Figure 12-4: Connection to the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC and Ethernet Statistic Core www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 119: Connection Of The Plb To The Edk For Logicore Ip Ethernet Macs

    Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Figure 12-4 illustrates the connection of the Ethernet AVB Endpoint core to the EMAC when using the Ethernet Statistics core. This shares much in common with Figure 12-2; however, note the following additional points: •...
  • Page 120 Custom AV logic traffic Ethernet client PHY I/F Legacy Custom Legacy logic traffic Figure 12-5: Connection of the Ethernet AVB Endpoint Core into an Embedded Processor Sub-system www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 121 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Figure 12-5 can be implemented using the Xilinx tool set using two methods: • “Using an EDK Project Top Level” • “Using an ISE Software Top-Level Project” Using an EDK Project Top Level...
  • Page 122 Custom AV logic traffic Ethernet client PHY I/F Legacy Custom Legacy logic traffic Figure 12-7: Connection into an Embedded Processor Sub-system with an ISE Software Top-Level Project www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 123 Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs Figure 12-7 shows the implementation using an ISE® software top-level project. In this hierarchy, the embedded processor subsystem is created using an EDK project containing only the blocks illustrated in the EDK tool domain block. This EDK project is not the top level of the system and is instantiated as a black box subcomponent in a standard ISE software project as illustrated.

  • Page 124: Using The Xilinx Xps Locallink Tri-Mode Ethernet Mac

    Chapter 12: System Integration Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC The Ethernet AVB Endpoint core should be generated in the “EDK pcore Format” when connecting to the XPS LocalLink Tri-Mode Ethernet MAC core (xps_ll_temac). Introduction The xps_ll_temac is delivered with data path FIFO’s (of configurable depth), optional TCP/IP Offload Engine (TOE) logic and various other optional features, all of which can be connected to Scatter Gather Direct Memory Access (DMA) Engines.

  • Page 125: System Overview: Avb Capable Xps_Ll_Temac

    Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC System Overview: AVB capable xps_ll_temac X-Ref Target - Figure 12-8 EDK Tool Domain BRAM lmb_bram_if_cntlr Microblaze MPMC xps_intc xps_uartlite pcore Ethernet XPS_LL_TEMAC Endpoin LocalLink MDIO interr upt_ptp_timer interrupt_ptp_tx interrupt_ptp_rx pcore Custom AV logic...

  • Page 126: Ethernet Avb Endpoint Connections

    “AV Traffic Interface” remains unconnected and is therefore available for custom logic. All connections must be made in the EDK environment; please refer to Xilinx Platform Studio documentation. Extracts from a .mhs file will be included at the end of this section to further illustrate these connections.

  • Page 127: Mhs File Syntax

    Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC X-Ref Target - Figure 12-9 Ethernet AVB Endpoint XPS LocalLink pcore Tri-Mode Ethernet MAC (xps_ll_temac) tx_clk Temac0AvbTxClk Temac0AvbTxClkEn tx_clk_enable Avb2Mac0TxData[7:0] tx_data[7:0] Avb2Mac0TxDataValid Transmitter I/F tx_data_valid Avb2Mac0TxUnderrun tx_underrun tx_ack Mac02AvbTxAck rx_clk Temac0AvbRxClk rx_clk_enable...
  • Page 128 PORT Avb2Temac0RxData = Avb2Temac0RxData PORT Avb2Temac0RxDataValid = Avb2Temac0RxDataValid PORT Avb2Temac0RxFrameGood = Avb2Temac0RxFrameGood PORT Avb2Temac0RxFrameBad = Avb2Temac0RxFrameBad BEGIN eth_avb_endpoint PARAMETER INSTANCE = eth_avb_endpoint_0 PARAMETER HW_VER = 2.02.a PARAMETER C_MEM0_BASEADDR = 0xcc000000 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 129 Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC PARAMETER C_MEM0_HIGHADDR = 0xcc00ffff BUS_INTERFACE SPLB = mb_plb PORT reset = sys_periph_reset # Connect as per Figure 12-9 PORT tx_clk = Temac0AvbTxClk PORT tx_clk_en = Temac0AvbTxClkEn PORT rx_clk = Temac0AvbRxClk PORT rx_clk_en = Temac0AvbRxClkEn...

  • Page 130: Using The Xilinx Axi Ethernet Mac

    Chapter 12: System Integration Using the Xilinx AXI Ethernet MAC The Ethernet AVB Endpoint will be enabled in the AXI_Ethernet LogiCORE by setting the parameter C_AVB=1 in EDK version 12.3 or later. If you have generated the AXI_Ethernet LogiCORE (with the parameter C_AVB set to “1”),...

  • Page 131: Chapter 13: Software Drivers

    If the core is acting as clock master, the software drivers delivered with the core periodically sample the current value of the RTC and transmit this value to every device on the network using the P802.1 defined Sync and Follow-Up PTP packets. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 132: Clock Slave

    “Ethernet AVB Endpoint Setup” • “Starting and Stopping the AVB Drivers” Note: Unless you are already familiar with the Xilinx Embedded Development Kit (EDK), see the EDK documentation to follow the steps described. Driver Instantiation Software driver instantiation for the Ethernet AVB Endpoint core follows the standard EDK model used for all EDK IP cores and as recommended for all user defined pcores (see documentation).

  • Page 133: Interrupt Service Routine Connections

    • needs to call the function interrupt_ptp_timer XAvb_PtpTimerInterruptHandler() • needs to call the function XAvb_PtpRxInterruptHandler() interrupt_ptp_rx Again, see the provided software example file that performs these steps. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 134: Core Initialization

    When connecting to the XPS LocalLink Tri-Mode Ethernet MAC (xps_ll_temac), available in EDK, the MAC is delivered with its own drivers and the functionality of this subsection is not required. The Xilinx LogiCORE™ IP “Tri-Mode Ethernet MACs” require initialization of the MDIO clock frequency (the MDC signal) and requires specific non-default configuration (VLAN enabled, Flow Control disabled).
  • Page 135 XAvb_Config *AvbConfigPtr; /** Setup the handler that will be called if the PTP drivers * identify a possible discontinuity in GrandMaster time. */ XAvb_SetGMDiscontinuityHandler(&Avb, GMDiscontinuityHandler, &Avb); /** ... */ /*****************************************************************/ Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 136: Starting And Stopping The Avb Drivers

    The software example included will halt the drivers whenever the Ethernet PHY Auto- Negotiation indicates that it has lost the link, or has negotiation to an unsupported ethernet mode (for example, half duplex). www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 137: Chapter 14: Quick Start Example Design

    The quick start steps provided in this chapter let you quickly generate an Ethernet AVB Endpoint core, run the design through implementation with the Xilinx tools, and simulate the design using the provided demonstration test bench. For detailed information about the Standard CORE Generator example design, see Chapter 15, “Detailed Example Design...
  • Page 138 Chapter 14: Quick Start Example Design The Ethernet AVB Endpoint example design has been tested using Xilinx® ISE® software v12.2, Cadence Incisive Enterprise Simulator (IES) v9.2, Mentor Graphics ModelSim v 6.5c, and Synopsys VCS and VCS MX 2009.12. X-Ref Target - Figure 14-1...

  • Page 139: Generating The Core

    For general help with starting and using CORE Generator software on your system, see the documentation supplied with the ISE software, including the CORE Generator Guide. These documents can be downloaded from: www.xilinx.com/support/software_manuals.htm Create a new project. For project options, select the following: ♦...
  • Page 140 The default core and its supporting files, including the example design, are generated in your project directly. For a detailed description of the design example files and directories, Chapter 15, “Detailed Example Design (Standard Format).” www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 141: Implementing The Example Design

    Implementing the Example Design Implementing the Example Design After the core is generated, the netlists and example design can be processed by the Xilinx implementation tools. The generated output files include several scripts to assist you in running the Xilinx software.

  • Page 142: Timing Simulation

    This section contains instructions for running a timing simulation of the Ethernet AVB Endpoint core using either VHDL or Verilog. A timing simulation model is generated when run through the Xilinx tools using the implementation script. You must implement the core before attempting to run timing simulation.

  • Page 143: Chapter 15: Detailed Example Design (Standard Format)

    This chapter provides detailed information on the core and example design, including a description of files and the directory structure generated by the Xilinx CORE Generator software, the purpose and contents of the provided scripts, the contents of the example HDL wrappers, and the operation of the demonstration test bench.

  • Page 144: Directory And File Contents

    Chapter 15: Detailed Example Design (Standard Format) <component_name>/drivers/v2_04_a Files for compiling the low-level drivers provided with the core drivers/avb_v2_04_a/data Data files for automatic integration into Xilinx Platform Studio drivers/avb_v2_04_a/examples An application example using the low-level driver files drivers/avb_v2_04_a/src Low-level driver source C files Directory and File Contents The core directories and their associated files are defined in the following tables.

  • Page 145: Project Directory>/

    An HDL file which sits in the place of an Ethernet MAC (an Ethernet MAC is required in a real system). This file loops back the data from the transmitter client to the receiver client. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 146: Component Name>/Implement

    Table 15-5: Implement Directory Name Description <project_dir>/<component_name>/implement implement.sh LINUX shell script that processes the example design through the Xilinx tool flow. “Implementation Scripts,” page 151 more information. implement.bat Windows batch file that processes the example design through the Xilinx tool flow.

  • Page 147: Implement/Results

    It is called by the macro file. simulate_mti.do simulate_ncsim.sh IES script file that compiles the Verilog or VHDL sources and runs the functional simulation to completion. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 148: Simulation/Timing

    VCS macro file that opens a wave window and adds signals of interest to it. It is called by script file. simulate_vcs.sh Back to Top www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 149: Component_Name>/Drivers/V2_04_A

    Current MDD file used, including the version of the tools interface. avb_v2_1_0.tcl Used to provide design rule checks within Xilinx Platform Studio. Back to Top drivers/avb_v2_04_a/examples The driver examples directory contains an application example using the low-level driver files.

  • Page 150: Drivers/Avb_V2_04_A/Src

    This defines the low level 0 device driver for the Ethernet AVB Endpoint core. xavb_hw.c This file partners the xavb_hw.h header file and implements the functions for which avb_hw.h contained a template. Back to Top www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 151: Implementation Scripts

    Design Entry project setting) and timing information in the form of SDF files. The Xilinx tool flow generates several output and report files that are saved in the following directory (which is created by the implement script): <project_dir>/<component_name>/implement/results...

  • Page 152: Timing Simulation

    Ethernet MAC, the PLB module should be replaced with an embedded processor, and the frame stimulus and checker modules should be replaced with the desired AV and Legacy client functionality. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 153: Top-Level Example Design Hdl

    (Destination Address, Source Address, Length/Type); the VLAN field is optional. Additionally, the length of the Ethernet frame can also be set using a generic. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 154: Ethernet Frame Checker

    This logic implements a simple logic shim to provide a frame loopback function at the MAC client Interface. This logic does NOT implement a MAC and should be replaced with a real MAC in any real implementations. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 155: Plb Module

    802.1AS (Precise Timing Protocol (PTP)) functionality. See Chapter 13, “Software Drivers” for detailed information about the provided software drivers. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...

  • Page 156: Demonstration Test Bench

    This should illustrate the bandwidth policing functionality of the core, which should only allow the AV frames to consume a maximum of 75% of the overall bandwidth. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 157: Customizing The Test Bench

    = 1'b0; // VLAN fields are not used so the following parameter is n/a parameter [15:0] LEGACY_VLAN_DATA = 16'h0000; // Use a Generic Type field parameter [15:0] LEGACY_TYPE_FIELD = 16'h8000; Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 158 Module Tx Frame Ethernet Stimulus Legacy Traffic Endpoint Core Statistic Legacy Gathering Traffic Rx Frame Checker Rx Frame Checker AV T raffic Interrupts Module Figure 15-3: Simulator Wave Window Contents www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...
  • Page 159 <component name>/doc Product documentation MyProcessorIPLib/pcores/eth_avb_endpoint_v2_04_a core netlist and HDL for the pcore pcores/eth_avb_endpoint_v2_04_a/data Data files for automatic integration into Xilinx Platform Studio pcores/eth_avb_endpoint_v2_04_a/hdl/vhdl VHDL wrapper file for the core netlist to enable integration into Platform Studio pcores/eth_avb_endpoint_v2_04_a/netlist The Ethernet AVB Endpoint core netlist...

  • Page 160: Chapter 16: Detailed Example Design (Edk Format)

    The <component name> directory contains the release notes file provided with the core, which may include last-minute changes and updates. Table 16-2: Component Name Directory Name Description <project_dir>/<component_name> eth_avb_endpoint_readme.txt Core release notes file. Back to Top www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 161: Component Name>/Doc

    Ethernet AVB Endpoint User Guide Back to Top <component name>/MyProcessorIPLib This is the route directory which should be imported into the Xilinx Embedded Development Kit. MyProcessorIPLib/pcores/eth_avb_endpoint_v2_04_a A directory containing the pcore HDL and netlist hardware components for the Ethernet AVB Endpoint core and associated supporting files.

  • Page 162: Pcores/Eth_Avb_Endpoint_V2_04_A/Hdl/Vhdl

    Netlist for the core that was synthesized during core generation Back to Top MyProcessorIPLib/drivers/avb_v2_04_a A directory containing the software device drivers for the Ethernet AVB Endpoint core and associated supporting files. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 163: Drivers/Avb_V2_04_A/Data

    Current MDD file used, including the version of the tools interface. avb_v2_1_0.tcl Used to provide design rule checks within Xilinx Platform Studio. Back to Top drivers/avb_v2_04_a/examples The driver examples directory contains an application example using the low-level driver files.

  • Page 164: Drivers/Avb_V2_04_A/Src

    This defines the low-level 0 device driver for the Ethernet AVB Endpoint core. xavb_hw.c This file partners the xavb_hw.h header file and implements the functions for which avb_hw.h contained a template. Back to Top www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 165: Importing The Ethernet Avb Endpoint Core Into The Embedded Development Kit (Edk)

    Development Kit (EDK) You can import a generated Ethernet AVB Endpoint netlist into an EDK project by following the usual steps to import a black box IP. See the Xilinx Platform Studio documentation for information. After importing the generated netlist, the drivers can also be linked into the software application.
  • Page 166 Chapter 16: Detailed Example Design (EDK format) www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 167: Appendix A: Rtc Time Stamp Accuracy

    The 2nd time stamp is requested at 201 ns. The RTC has recently updated and so the sample taken will be of 200. This has an inaccuracy of 1 ns. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 168 X-Ref Target - Figure A-1 Time (ns) RTC Error (ns) Timestamp A Timestamp B (Error = 39 ns) (Error = 1 ns) Figure A-1: RTC Periodic Error www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 169: Rtc Sampling Error

    If the flip-flop samples logic ‘1’, the result is Timing Case 1; if the flip-flop samples logic ‘0’, Timing Case 2 results. The overall result of this is to obtain a single Reference Clock Period of uncertainty in the captured time stamp value. Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 170 RTC Reference Clock Take RTC Sample Sample TIMING CASE 2 MAC Tx/Rx clock toggle clock boundary RTC Reference Clock Take RTC Sample Sample Sampling uncertainty Figure A-3: Sampling Position Uncertainty www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

  • Page 171: Accuracy Resulting From The Combined Errors

    The request for the 2nd time stamp is made at 239 ns. This is very close to the rising edge of the 1st synchronization flip-flop in Figure A-2, so the situation is unpredictable: Ethernet AVB Endpoint User Guide www.xilinx.com UG492 September 21, 2010...
  • Page 172 For example, when using a 125 MHz clock source for the RTC, the maximum time stamp error will be 8 ns or less. www.xilinx.com Ethernet AVB Endpoint User Guide UG492 September 21, 2010...

Table of Contents