Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual page 121

Figure 12-5
•
•
Using an EDK Project Top Level
X-Ref Target - Figure 12-6
EDK Tool Domain
xps_intc
Figure 12-6: Connection into an Embedded Processor Sub-system with an EDK Top-level Project
Figure 12-6
Ethernet AVB Endpoint, Tri-Mode Ethernet MAC, and all custom logic blocks, must be
manually translated into pcores using the standard pcore approach described in
Platform Studio documentation.
the project.
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
can be implemented using the Xilinx tool set using two methods:
"Using an EDK Project Top Level"
"Using an ISE Software Top-Level Project"
BRAM
lmb_bram_if_cntlr
Microblaze
xps_uartlite
plb_port
interrupt_ptp_timer
interrupt_ptp_tx
interrupt_ptp_rx
pcore
Custom AV logic
pcore
Custom Legacy logic
shows the implementation using an EDK project. In this hierarchy, the
www.xilinx.com
Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs
PLB
pcore:
pcore
Ethernet
AVB
t
Endpoin
PLB
AV
traffic
I/F
Legacy
traffic
I/F
The standard EDK flow can then be implemented to build
pcore
TEMAC
Host I/F MDIO
MAC
Ethernet
client
PHY I/F
I/F
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