Timing Simulation; Example Design - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

Chapter 15: Detailed Example Design (Standard Format)

Timing Simulation

The test script is a ModelSim, IES, or VCS macro that automates the simulation of the test
bench and is in the following location:
The test script performs the following tasks:
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Example Design

Figure 15-1
Individual sub-blocks are described in the following sections.
X-Ref Target - Figure 15-1
Note:
demonstrate some of the functionality of the core, and does not create a realistic implementation. In
a real system the loopback module should be replaced with an Ethernet MAC, the PLB module
should be replaced with an embedded processor, and the frame stimulus and checker modules
should be replaced with the desired AV and Legacy client functionality.
152
<project_dir>/<component_name>/simulation/timing/
Compiles the SimPrim-based gate level netlist simulation model
Compiles the demonstration test bench
Starts a simulation of the test bench using back-annotated timing information (SDF)
Opens a Wave window and adds signals of interest
Runs the simulation to completion
illustrates the complete example design for the Ethernet AVB Endpoint.
Example Design Top Level
Tx Frame
Stimulus
Tx Frame
Stimulus
Rx Frame
Checker
Rx Frame
Checker
Figure 15-1: Example Design HDL for the Ethernet AVB Endpoint
The example design is designed to allow the core, in isolation, to be tested and to
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AV Traffic
Ethernet
AVB
Legacy
Endpoint
Traffic
Core
Legacy
Traffic
AV Traffic
Interrupts PLB
PLB
module
Ethernet AVB Endpoint User Guide
Loopback
Module
UG492 September 21, 2010