Xilinx LogiCORE Endpoint v2.4 Manuals

Manuals and User Guides for Xilinx LogiCORE Endpoint v2.4. We have 1 Xilinx LogiCORE Endpoint v2.4 manual available for free PDF download: User Manual

Xilinx LogiCORE Endpoint v2.4 User Manual (172 pages)

Brand: Xilinx | Category: Software | Size: 4 MB

Revision History

2
- Table of Contents
  3
Schedule of Figures

9
Schedule of Tables

13
Preface: about this Guide

17
- Guide Contents
  
  17
- Conventions
  
  18
  - Typographical
    18
  - Online Document
    19
  - List of Abbreviations
    20
Chapter 1: Introduction

23
- System Requirements
  
  23
- About the Core
  
  23
- Recommended Design Experience
  
  24
- Additional Core Resources
  
  24
- Technical Support
  
  24
- Feedback
  
  24
  - Ethernet AVB Endpoint Core
    24
  - Document
    25
Chapter 2: Licensing the Core

27
- Before You Begin
  
  27
- License Options
  
  27
  - Simulation Only
    27
  - Full System Hardware Evaluation
    27
  - Full
    28
- Obtaining Your License Key
  
  28
- Installing the License File
  
  28
Chapter 3: Overview of Ethernet Audio Video Bridging

29
- AVB Specifications
  
  30
  - P802.1As
    30
  - P802.1Qav
    31
  - P802.1Qat
    32
- Typical Implementation
  
  32
- Ethernet AVB GUI
  
  35
Chapter 4: Generating the Core

36
- Component Name
  36
- Core Delivery Format
  36
- Ethernet AVB GUI
  
  37
  - Number of PLB Masters
    37
  - PLB Base Address
    37
- Parameter Values in the XCO File
  
  38
- Output Generation
  
  38
Chapter 5: Core Architecture

39
- Standard CORE Generator Format
  
  40
- EDK Pcore Format
  
  41
- Functional Block Description
  
  42
  - PLB Interface
    42
  - AV Traffic Interface
    42
  - Legacy Traffic Interface
    42
  - Tx Arbiter
    43
  - Rx Splitter
    43
  - MAC Header Filters
    43
  - Precise Timing Protocol Blocks
    44
  - Software Drivers
    46
  - Tri-Mode Ethernet Macs
    46
- Core Interfaces
  
  47
  - Clocks and Reset
    47
  - Legacy Traffic Interface
    48
  - AV Traffic Interface
    49
  - Tri-Mode Ethernet MAC Client Interface
    50
  - Processor Local Bus (PLB) Interface
    52
  - Interrupt Signals
    55
  - PTP Signals
    56
Chapter 6: Ethernet AVB Endpoint Transmission

57
- Tx Legacy Traffic I/F
  
  57
  - Error Free Legacy Frame Transmission
    58
  - Errored Legacy Frame Transmission
    59
- Tx AV Traffic I/F
  
  59
- Tx Arbiter
  
  61
Chapter 7: Ethernet AVB Endpoint Reception

65
- Rx Splitter
  
  65
- Rx Legacy Traffic I/F
  
  65
- Rx AV Traffic I/F
  
  73
  - Error Free AV Traffic Reception
    73
  - Errored AV Traffic Reception
    74
Chapter 8: Real Time Clock and Time Stamping

75
Chapter 9: Precise Timing Protocol Packet Buffers

83
- Tx PTP Packet Buffer
  83
- Tx PTP Packet Buffer Rx PTP Packet Buffer
  
  83
Figure 9-2: Rx Ptp Packet Buffer

86
Chapter 10: Configuration and Status

87
Chapter 11: Constraining the Core

103
- Required Constraints
  
  103
  - Device, Package, and Speedgrade Selection
    103
  - I/O Location Constraints
    103
  - Placement Constraints
    103
  - Timing Constraints
    103
Chapter 12: System Integration

111
Chapter 13: Software Drivers

131
- Clock Master
  
  131
- Clock Slave
  
  132
- Software System Integration
  
  132
  - Driver Instantiation
    132
  - Interrupt Service Routine Connections
    133
  - Core Initialization
    134
  - Ethernet AVB Endpoint Setup
    134
  - Starting and Stopping the AVB Drivers
    136
Chapter 14: Quick Start Example Design

137
- Overview
  
  137
- Generating the Core
  
  139
- Implementing the Example Design
  
  141
- Simulating the Example Design
  
  141
  - Setting up for Simulation
    141
  - Functional Simulation
    141
  - Timing Simulation
    142
- What's Next
  
  142
Chapter 15: Detailed Example Design (Standard Format)

143
- Directory and File Contents
  
  144
  - Project Directory
    144
  - Project Directory>/<Component Name
    145
  - Component Name>/Doc
    145
  - Component Name>/Example Design
    145
  - Component Name>/Implement
    146
  - Implement/Results
    147
  - Component Name>/Simulation
    147
  - Simulation/Functional
    147
  - Simulation/Timing
    148
  - Component_Name>/Drivers/V2_04_A
    149
  - Drivers/Avb_V2_04_A/Data
    149
  - Drivers/Avb_V2_04_A/Examples
    149
  - Drivers/Avb_V2_04_A/Src
    150
- Implementation Scripts
  
  151
- Simulation Scripts
  
  151
  - Functional Simulation
    151
  - Timing Simulation
    152
- Example Design
  
  152
  - Top-Level Example Design HDL
    153
  - Ethernet Frame Stimulus
    153
  - Ethernet Frame Checker
    154
  - Loopback Module
    154
  - PLB Module
    155
  - Demonstration Test Bench
    156
  - Customizing the Test Bench
    157
Chapter 16: Detailed Example Design (EDK Format)

160
- Directory and File Contents
  
  160
  - Project Directory
    160
  - Project Directory>/<Component Name
    160
  - Component Name>/Doc
    161
  - Component Name>/Myprocessoriplib
    161
  - Myprocessoriplib/Pcores/Eth_Avb_Endpoint_V2_04_A
    161
  - Pcores/Eth_Avb_Endpoint_V2_04_A/Data
    161
  - Pcores/Eth_Avb_Endpoint_V2_04_A/Hdl/Vhdl
    162
  - Pcores/Eth_Avb_Endpoint_V2_04_A/Netlist
    162
  - Myprocessoriplib/Drivers/Avb_V2_04_A
    162
  - Drivers/Avb_V2_04_A/Data
    163
  - Drivers/Avb_V2_04_A/Examples
    163
  - Drivers/Avb_V2_04_A/Src
    164
- Importing the Ethernet AVB Endpoint Core into the Embedded Development Kit (EDK)
  
  165
Appendix A: RTC Time Stamp Accuracy

167
Time Stamp Accuracy

167

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Xilinx LogiCORE Endpoint v2.4 Manuals

Xilinx LogiCORE Endpoint v2.4 User Manual (172 pages)

Table of Contents

Revision History

Schedule of Figures

Schedule of Tables

Preface: about this Guide

Guide Contents

Conventions

Chapter 1: Introduction

System Requirements

About the Core

Recommended Design Experience

Additional Core Resources

Technical Support

Feedback

Chapter 2: Licensing the Core

Before You Begin

License Options

Obtaining Your License Key

Installing the License File

Chapter 3: Overview of Ethernet Audio Video Bridging

AVB Specifications

Typical Implementation

Ethernet AVB GUI

Chapter 4: Generating the Core

Ethernet AVB GUI

Parameter Values in the XCO File

Output Generation

Chapter 5: Core Architecture

Standard CORE Generator Format

EDK Pcore Format

Functional Block Description

Core Interfaces

Chapter 6: Ethernet AVB Endpoint Transmission

Tx Legacy Traffic I/F

Tx AV Traffic I/F

Tx Arbiter

Chapter 7: Ethernet AVB Endpoint Reception

Rx Splitter

Rx Legacy Traffic I/F

Rx AV Traffic I/F

Chapter 8: Real Time Clock and Time Stamping

Real Time Clock

Time Stamping Logic

IEEE1722 Real Time Clock Format

Chapter 9: Precise Timing Protocol Packet Buffers

Tx PTP Packet Buffer Rx PTP Packet Buffer

Figure 9-2: Rx Ptp Packet Buffer

Chapter 10: Configuration and Status

Figure 10-1: Single Read Transaction

Processor Local Bus Interface

PLB Address Map and Register Definitions

Chapter 11: Constraining the Core

Required Constraints

Chapter 12: System Integration

Using the Xilinx Logicore IP Tri-Mode Ethernet Macs

Figure 12-2: Connection to the Tri-Mode Ethernet Mac and Ethernet Statistic Cores

Using the Xilinx XPS Locallink Tri-Mode Ethernet MAC

Using the Xilinx AXI Ethernet MAC

Chapter 13: Software Drivers

Clock Master

Clock Slave

Software System Integration

Chapter 14: Quick Start Example Design

Overview

Generating the Core

Implementing the Example Design

Simulating the Example Design

What's Next

Chapter 15: Detailed Example Design (Standard Format)

Directory and File Contents

Implementation Scripts

Simulation Scripts

Example Design

Chapter 16: Detailed Example Design (EDK Format)

Directory and File Contents

Importing the Ethernet AVB Endpoint Core into the Embedded Development Kit (EDK)

Appendix A: RTC Time Stamp Accuracy

Time Stamp Accuracy