Generating The Core - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

Generating the Core

This section provides detailed instructions for generating the Ethernet AVB Endpoint
example design core.
To generate the core:
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Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Start the CORE Generator™ tool.
For general help with starting and using CORE Generator software on your system,
see the documentation supplied with the ISE software, including the CORE Generator
Guide. These documents can be downloaded from:
www.xilinx.com/support/software_manuals.htm
Create a new project.
For project options, select the following:
♦
A Virtex®-6, Virtex-5, Spartan®-3, Spartan-3E, Spartan-3A/3A DSP or Spartan-6
device to generate the default Ethernet AVB Endpoint core.
♦
In the Design Entry section, select VHDL or Verilog; then select Other for Vendor.
Locate the Ethernet AVB Endpoint core in the taxonomy tree, listed under one of the
following:
♦
Automotive & Industrial/Automotive
♦
Communications & Networking/Ethernet
♦
Communications & Networking/Networking
♦
Communications & Networking/Telecommunications
Double-click the core name. A message may appear to indicate the limitations of the
Simulation Only Evaluation license.
Click OK; the core customization screen appears.
www.xilinx.com
Generating the Core
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