Component Name>/Implement - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

Chapter 15: Detailed Example Design (Standard Format)
Table 15-4: Example Design Directory (Cont'd)
<component name>/implement
The implement directory contains the core implementation script files.
Table 15-5: Implement Directory
146
Name
rx_frame_checker.v[hd]
plb_client_logic.v[hd]
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Name
<project_dir>/<component_name>/implement
implement.sh
implement.bat
xst.prj
xst.scr
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Description
An HDL file which is capable of receiving
Ethernet frames at maximum line rate.
This will check the data contained in each
Ethernet frame received against a
predictable pattern. This file partners the
tx_frame_stimulus file.
An HDL file that sits in the place of an
embedded microprocessor (an
embedded microprocessor is required in
a real system), which provides stimulus
to the PLB, performing write and reads
that initiate PTP frame transmission.
Description
LINUX shell script that processes the
example design through the Xilinx tool flow.
See "Implementation Scripts," page 151
more information.
Windows batch file that processes the
example design through the Xilinx tool flow.
See "Implementation Scripts," page 151
more information.
XST project file for the example design
(VHDL only); it enumerates all of the VHDL
files that need to be synthesized.
XST script file for the example design.
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
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