Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual page 113

Connections Without Ethernet Statistics
X-Ref Target - Figure 12-1
Ethernet AVB Endpoint
Core Netlist
tx_clk
tx_clk_en
tx_data[7:0]
tx_data_valid
tx_underrun
tx_ack
rx_clk
rx_clk_en
rx_data[7:0]
rx_data_valid
rx_frame_good
rx_frame_bad
host_opcode[1:0]
host_addr[9:0]
host_wr_data[31:0]
host_req
host_miim_sel
host_miim_rdy
host_rd_data_mac[31:0]
host_rd_data_stats[31:0]
host_stats_lsw_rdy
host_stats_msw_rdy
host_clk
host_clk
Figure 12-1: Connection to the Tri-Mode Ethernet MAC Core (without Ethernet Statistics)
Figure 12-1
Mode Ethernet MAC (TEMAC) core when not using the Ethernet Statistics core.
Figure 12-1
in
All connections, as shown, are logic-less connections. Because the AVB standard does not
include support for half-duplex or flow control operation, the relevant half-duplex/flow-
control signals of the TEMAC can be left unused: inputs can be tied to logic 0, outputs can
be left unconnected.
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
GND
illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri-
provides detail for the connections between the two cores which were shown
Figure 5-1.
www.xilinx.com
Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs
TEMAC Block-level Wrapper
(from TEMAC Example Design)
pause_req
pause_val[15:0]
GND
tx_clk
tx_clk_en
tx_data[7:0]
tx_data_valid
tx_underrun
tx_ack
NC
tx_collision
NC
tx_retransmit
tx_ifg_delay[7:0]
GND
rx_clk
rx_clk_en
rx_data[7:0]
rx_data_valid
rx_frame_good
rx_frame_bad
host_opcode[1:0]
host_addr[9:0]
host_wr_data[31:0]
host_req
host_miim_sel
host_miim_rdy
host_rd_data[31:0]
host_clk
tx_statistics_valid NC
NC
tx_statistics_vector[31:0]
rx_statistics_valid NC
NC
rx_statistics_vector[27:0]
113