Project Directory>/<Component Name; Component Name>/Doc; Component Name>/Example Design - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

<project directory>/<component name>
The <component name> directory contains the release notes file provided with the core,
which may include last-minute changes and updates.
Table 15-2: Component Name Directory
<component name>/doc
The doc directory contains the PDF documentation provided with the core.
Table 15-3: Doc Directory
<component name>/example design
The example design directory contains the example design files provided with the core.
For more information, see
Table 15-4: Example Design Directory
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Name
eth_avb_endpoint_readme.txt
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Name
<project_dir>/<component_name>/doc
eth_avb_endpoint_ds677.pdf
eth_avb_endpoint_ug492.pdf
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Name
<project_dir>/<component_name>/example_design/
<component_name>_example_design.ucf
<component_name>_example_design.v[hd]
tx_frame_stimulus.v[hd]
temac_loopback_shim.v[hd]
www.xilinx.com
<project_dir>/<component_name>
Core release notes file
Ethernet AVB Endpoint Data Sheet
Ethernet AVB Endpoint User Guide
"Example Design," page
Example User Constraints File (UCF)
provided for the example design.
Top-level file that allows the example
design to be implemented in a device as a
standalone design.
An HDL file which is capable of
producing Ethernet frames at maximum
line-rate and containing a predictable
pattern in the data field.
An HDL file which sits in the place of an
Ethernet MAC (an Ethernet MAC is
required in a real system). This file loops
back the data from the transmitter client
to the receiver client.
Directory and File Contents
Description
Description
152.
Description
145