Chapter 11: Constraining The Core; Required Constraints; Device, Package, And Speedgrade Selection; I/O Location Constraints - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

Constraining the Core
This chapter defines the Ethernet AVB Endpoint core constraints. An example user
constraints file (UCF) is provided for the core and the HDL example design.

Required Constraints

Device, Package, and Speedgrade Selection

The Ethernet AVB Endpoint core can be implemented in Spartan®-3, Spartan-3E, Spartan-
3A/3A DSP, Spartan-6, Virtex®-5 and Virtex-6 devices that are large enough to
accommodate the core, and meet the following speed grades:
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I/O Location Constraints

No specific I/O location constraints are required.

Placement Constraints

No specific placement constraints are required.

Timing Constraints

The core can have up to five separate clock domains:
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These clock nets and the signals within the core that cross these clock domains must be
constrained appropriately in a UCF.
Sections of UCF syntax are used in the following descriptions to provide examples.
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
-1 for Virtex-5 and Virtex-6 devices
-2 for Spartan-6 devices
-4 for all Spartan-3 devices
plb_clk for the main EDK PLB and processor clock frequency
host_clk for the management interface logic of the connected Tri-Mode Ethernet
MAC
tx_clk for the MAC transmitter clock domain
rx_clk for the MAC receiver clock domain
rtc_clk for the"Real Time Clock"
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reference frequency
Chapter 11
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