Error Free Legacy Frame Reception - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

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Chapter 7: Ethernet AVB Endpoint Reception

Error Free Legacy Frame Reception

X-Ref Target - Figure 7-1
rx_clk
rx_clk_enable
legacy_rx_data[7:0]
legacy_rx_data_valid
Figure 7-1
accepted by the
accept data at any time; there is no buffering within the core to allow for latency in the
receive client. After frame reception begins, data is transferred on consecutive clock
enabled cycles to the receive client until the frame is complete. The core asserts the
legacy_rx_frame_good signal to indicate that the frame was intended for the legacy
traffic client and was successfully received without error.
66
legacy_rx_frame_good
legacy_rx_frame_bad
Figure 7-1: Normal Frame Reception across the Legacy Traffic Interface
illustrates the timing of a normal inbound error free frame transfer that has been
"Legacy MAC Header Filters"
www.xilinx.com
DA
SA
L/T
The legacy client must be prepared to
Ethernet AVB Endpoint User Guide
DATA
UG492 September 21, 2010

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