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Rx PTP Packet Buffer
The Rx PTP packet buffer is illustrated in
hold each received PTP frame. The software drivers, via the PLB configuration bus, can
then read and decode the contents of the received PTP frames.
The PTP packet buffer is implemented in dual-port block RAM. Port A of the block RAM is
connected to the PLB configuration bus: all addresses in the buffer can be read (writes are
not allowed). Port B of the block RAM is connected to the Rx Splitter module, which routes
all received PTP frames into the Rx PTP Packet Buffer.
The Rx PTP Packet Buffer is divided into sixteen identical buffer sections as illustrated.
Each section contains 256 bytes, which are formatted as follows:
•
•
Following reset, the first received PTP frame will be written into Buffer Number 0. The
next subsequent received PTP frame will be written into the next available buffer - in this
case number 1. This process continues with buffer number 2, 3, then 4, and so forth, being
used. After receiving the 16th PTP frame (which would have been stored into buffer
number 15), the count will be reset, and then buffer number 0 will be overwritten with the
next received PTP frame. For this reason, at any one time, the Rx PTP Packet Buffer is
capable of storing the most recently received sixteen PTP frames.
Following the completion of PTP frame reception, a dedicated interrupt signal,
interrupt_ptp_rx, will be generated by the core. On the assertion of the interrupt, the
captured timestamp will already be available in the upper four bytes of the buffer, and the
rx_packet field of the
filled Buffer Number.
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
The PTP frame data itself is stored from address 0 onwards: the entire MAC frame
from the Destination Address onwards will be written (with the exception of the FCS
field which will have been removed by the TEMAC). The amount of addresses used
will be dependent on the particular PTP frame size, which is different for each PTP
frame type. Each PTP buffer provides a maximum of 252 bytes (more than that
required for the largest PTP frame). Should an illegally oversized PTP frame be
received, the first 252 bytes will be captured and stored - other bytes will be lost.
The top four addresses of each buffer, from address 0xFC to 0xFF are reserved for a
timestamp field. At the beginning of PTP frame reception, the
will sample the
"Real Time Clock."
captured timestamp will automatically be written into this location to accompany the
frame for which it was taken.
"Rx PTP Packet Control Register"
www.xilinx.com
Figure
9-2. This provides working memory to
Following the end of PTP frame reception, this
will indicate the most recently
Rx PTP Packet Buffer
"Time Stamping Logic"
85
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