Accuracy Resulting From The Combined Errors - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

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Accuracy Resulting from the Combined Errors

The section
RTC reference clock period can result as a consequence of the RTC itself. The section
Sampling Error"
RTC reference clock domain, can result in one RTC reference clock period of uncertainty.
Figure A-4
Again, the worst case clock period of 40 ns is illustrated.
X-Ref Target - Figure A-4
In
is variable. For example:
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
"RTC Real Time Instantaneous Error"
describes how the position of the time stamp request, as observed in the
attempts to illustrate the result of the combination of these two types of error.
RTC
0
40
40
0
-40
RTC Error (ns)
Timing Case 1
Figure A-4: Overall Time Stamp Accuracy
Figure
A-4, two time stamps of the RTC are sampled. The figure shows that the accuracy
The request for the 1st time stamp is made at 60 ns. Because the time to the next RTC
reference clock is 20 ns, this will not violate the setup time for the 1st synchronization
flip-flop in
Figure
A-2. Therefore, on the next RTC reference clock, the sample will be
taken as 40 ns (resulting in an error of 20 ns which is entirely due to the
Time Instantaneous
Error").
The request for the 2nd time stamp is made at 239 ns. This is very close to the rising
edge of the 1st synchronization flip-flop in
unpredictable:
www.xilinx.com
describes how a maximum error of one
80
120
160
80
120
160
Figure
Time Stamp Accuracy
200
240
200
240
Sampling
uncertainty
Timing Case 2
"RTC Real
A-2, so the situation is
"RTC
Time (ns)
171

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