Plb Module - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

PLB Module

The following files describe the logic for the PLB module.
VHDL
Verilog
The PLB module connects to the PLB interface of the core and performs the following
functions:
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This functionality is related to the normal operation of a PTP clock master in that the logic
results in a transmission of PTP Sync/Follow-Up pair of frames being sent periodically.
However, the functionality is greatly simplified and none of the relevant variable PTP
Sync/Follow-up fields are correctly set.
Note:
drivers are provided to be run on an embedded processor, which performs full 802.1AS (Precise
Timing Protocol (PTP)) functionality. See
about the provided software drivers.
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
<project_dir>/<component_name>/example_design/plb_client_logic.vhd
<project_dir>/<component_name>/example_design/plb_client_logic.v
Initialization. A state machine writes to the RTC configuration space to set the RTC
running at the correct frequency following reset/power-up.
PTP Timer Interrupt Service Routine. When the interrupt_ptp_timer is
asserted, a state machine requests transmission of a PTP sync frame, then clears the
interrupt.
PTP Transmit Interrupt Service Routine. When interrupt_ptp_tx is asserted (a
PTP frame has been transmitted), the state machine reads from the PTP Tx
Control/Status register to determine the type of PTP frame sent. If it was a sync
frame, it then requests a follow-up frame to be sent. For any other PTP frame type, no
action is taken. Reading from the PTP Tx Control/Status register clears the interrupt.
PTP Receive Interrupt Service Routine. When interrupt_ptp_rx is asserted (a
PTP frame has been received), the state machine reads from the PTP Rx
Control/Status register to determine which of the PTP frame buffers the received
frame will be stored in; this read also clears the interrupt. In this simple
demonstration, nothing further is performed.
The real intent for the PLB interface is for connection into the EDK environment; software
www.xilinx.com
Chapter 13, "Software Drivers"
Example Design
for detailed information
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