Demonstration Test Bench - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

Chapter 15: Detailed Example Design (Standard Format)

Demonstration Test Bench

Figure 15-2
VHDL or Verilog program for exercising the example design and the core.
X-Ref Target - Figure 15-2
The following files describe the top level of the demonstration test bench:
VHDL
Verilog
The top-level test bench entity instantiates the example design for the core, which is the
Device Under Test (DUT). The test bench provides clocks and resets, and gathers statistics
for the duration of the simulation. A final statistic report is created at the end of the
simulation run time that contains the following:
•
•
•
•
156
illustrates the Ethernet AVB Endpoint demonstration test bench, a simple
Demonstration Test Bench
Example Design Top Level
Clock
and
Reset
generation
Statistic
Gathering
Figure 15-2: Ethernet AVB Endpoint Demonstration Test Bench
<project_dir>/<component_name>/simulation/demo_tb.vhd
<project_dir>/<component_name>/simulation/demo_tb.v
The number of PTP frames transmitted and received
The number of AV frames transmitted and received
The number of legacy frames transmitted and received.
All transmitted frame statistics should exactly match the received frame statistics for
each particular frame type; if this is not the case, an error message is issued.
Finally, the test bench estimates the percentage of overall Ethernet line rate consumed
by each of the three types. This should illustrate the bandwidth policing functionality
of the core, which should only allow the AV frames to consume a maximum of 75% of
the overall bandwidth.
www.xilinx.com
Tx frame AV traffic
stimulus
Tx frame
Ethernet
stimulus
legacy
Endpoint
traffic
LogiCORE
legacy
Rx frame
traffic
checker
Rx frame
checker
AV traffic
Interrupts
module
Ethernet AVB Endpoint User Guide
loopback
module
AVB
PLB
PLB
UG492 September 21, 2010