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Chapter 10: Configuration and Status
Tx Arbiter Send Slope Control Register
The sendSlope variable is defined in IEEE P802.1 Qav to be the rate of change of credit, in
bits per second, when the value of credit is decreasing (during AV packet transmission).
Together with the
limit of the bandwidth that is reserved for AV traffic; this will be enforced by the
Arbiter."
traffic. See the IEEE P802.1 Qav specification and
Table 10-4: Tx Arbiter Send Slope Control Register (PLB_base_address + 0x200C)
Tx Arbiter Idle Slope Control Register
The idleSlope variable is defined in IEEE802.1Qav to be the rate of change of credit, in bits
per second, when the value of credit is increasing (whenever there is no AV packet
transmission). Together with the
define the maximum limit of the bandwidth that is reserved for AV traffic; this is enforced
by the
for the AV traffic. See the IEEE P802.1 Qav specification and
information.
Table 10-5: Tx Arbiter Idle Slope Control Register (PLB_base_address + 0x2010)
RTC Offset Control Registers
Table 10-6
Clock,"
can be used to set the initial value following power-up. When in PTP clock slave mode, the
"Software Drivers"
This register and the registers defined in
three offset values will be loaded into the RTC counter logic simultaneously following a
write to this nanosecond offset register.
Table 10-6: RTC Nanoseconds Field Offset (
Table 10-7
"Real Time Clock,"
mode, this can be used to set the initial value following power-up. When in PTP clock slave
mode, the
94
"Tx Arbiter Idle Slope Control Register,"
The default values allow the maximum bandwidth proportion of 75% for the AV
Bit no
Default
Access
19-0
2048
R/W
31-20
0
RO
The default values allow the maximum bandwidth proportion of 75%
"Tx Arbiter."
Bit no
Default
Access
31-20
0
RO
19-0
6144
R/W
describes the offset control register for the nanoseconds field of the
used to force step changes into the counter. When in PTP clock master mode, this
will use this register to implement the periodic step corrections.
Bit no
Default
Access
29-0
0
31-30
0
describes the offset control register for the lower 32-bits of seconds field of the
used to force step changes into the counter. When in PTP clock master
"Software Drivers"
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"Tx Arbiter"
The value of
"sendSlope"
Unused
"Tx Arbiter Send Slope Control Register,"
Unused
The value of
"idleSlope"
Table 10-7
and in
PLB_base_address
R/W
30-bit offset value for the RTC nanoseconds field. Used
by the microprocessor to initialize the RTC, then
afterwards to perform the regular RTC corrections
(when in slave mode).
RO
Unused
use this register to implement the periodic step corrections.
registers define the maximum
"Tx
for more information.
Description
two registers
"Tx Arbiter"
for more
Description
"Real Time
Table 10-8
are linked. These
+ 0x2800)
Description
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
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