Mhs File Syntax - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

X-Ref Target - Figure 12-9

MHS File Syntax

The following code extracts are taken from an XPS project which connected the Ethernet
AVB Endpoint core to an instance of the xps_ll_temac. This design targeted the Virtex-5
family and implemented the xps_ll_temac using an Embedded Tri-Mode Ethernet MAC
macro.
This MHS syntax is included for illustration/guideline purposes. It is recommended that
the XPS GUI is used to import and connect pcore peripherals rather than by manually
editing the .mhs file for a given project. Please refer to
documentation.
Certain lines are highlighted and commented to draw attention.
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Ethernet AVB Endpoint
pcore
tx_clk_enable
MAC tx_data[7:0]
Transmitter I/F tx_data_valid
tx_underrun
rx_clk_enable
rx_data[7:0]
MAC
rx_data_valid
Receiver I/F
rx_frame_good
rx_frame_bad
legacy_tx_data[7:0]
Legacy
legacy_tx_data_valid
Transmitter I/F
legacy_tx_underrun
legacy_tx_ack
legacy_rx_data[7:0]
Legacy
legacy_rx_data_valid
Recevier I/F
legacy_rx_frame_good
legacy_rx_frame_bad
Figure 12-9: Connection to the XPS LocalLink Tri-Mode Ethernet MAC
www.xilinx.com
Using the Xilinx XPS LocalLink Tri-Mode Ethernet MAC
tx_clk
tx_ack
rx_clk
Xilinx Platform Studio
XPS LocalLink
Tri-Mode Ethernet MAC
(xps_ll_temac)
Temac0AvbTxClk
Temac0AvbTxClkEn
Avb2Mac0TxData[7:0]
Avb2Mac0TxDataValid
Avb2Mac0TxUnderrun
Mac02AvbTxAck
Temac0AvbRxClk
Temac0AvbRxClkEn
Mac02AvbRxData[7:0]
Mac02AvbRxDataValid
Mac02AvbRxFrameGood
Mac02AvbRxFrameBad
Temac02AvbTxData[7:0]
Temac02AvbTxDataValid
Temac02AvbTxUnderrun
Avb2Temac0TxAck
Avb2Temac0RxData[7:0]
Avb2Temac0RxDataValid
Avb2Temac0RxFrameGood
Avb2Temac0RxFrameBad
127