Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual page 53

PLB Interface
Table 5-9
specification. Shaded rows represent signals not used by this core; inputs are ignored and
outputs are tied to a constant. These signals are synchronous to PLB_clk; see
Resets"
Table 5-9: PLB Signals
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
defines the signals on the PLB bus. For detailed information, see the IBM PLB
for additional information.
PIN Name
PLB_clk
PLB_reset
PLB_ABus[0:31]
PLB_UABus[0:31]
PLB_PAvaild
PLB_SAValid
PLB_rdPrim
PLB_wrPrim
PLB_masterID
[0:log2(NUM_MASTERS)]
PLB_abort
PLB_busLock
PLB_RNW
PLB_BE[0:3]
PLB_MSize[0:1]
PLB_size[0:3]
PLB_type[0:2]
PLB_TAttribute[0:15]
PLB_lockErr
PLB_wrDBus[0:31]
PLB_wrBurst
PLB_rdBurst
PLB_rdPendReq
PLB_wrPendReq
PLB_rdPendPri[0:1]
www.xilinx.com
Direction
Input Reference clock for the PLB
Input Reset for the PLB, synchronous to
PLB_clk
input PLB address bus
Input PLB upper address bus
Input PLB primary address valid indicator
Input Unused. PLB secondary address valid
indicator.
Input Unused. PLB secondary to primary read
request indicator.
Input Unused. PLB secondary to primary write
request indicator.
Input PLB current master identifier
Input PLB abort request indicator
Input Unused. PLB bus lock.
Input PLB read not write
Input PLB byte enables
Input PLB master data bus size
Input PLB transfer size. Only support size 0.
Input PLB transfer type. Only support type 0.
Input Unused. PLB transfer attribute bus.
Input Unused. PLB lock error indicator.
Input PLB write data bus
Input PLB write burst transfer indicator.
Input PLB read burst transfer indicator.
Input Unused. PLB pending read request
priority.
Input Unused. PLB pending write request
priority.
Input Unused. PLB pending read bus request
indicator.
Core Interfaces
"Clocks and
Description
53