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MAC Receiver Interface
These signals connect directly to the identically named Tri-Mode Ethernet MAC signals
and are synchronous to rx_clk
Table 5-7: Tri-Mode Ethernet MAC Receiver Interface
MAC Management Interface
This interface is only present when the core is generated in
Format", designed for connection to LogiCORE IP Tri-Mode Ethernet MAC devices.
When present, these signals connect directly to the identically named LogiCORE IP Tri-
Mode Ethernet MAC signals (except where stated in
host_clk. When present, all MAC configuration and MDIO register space is address
mapped into the PLB of the Ethernet AVB Endpoint core. A logic shim automatically drives
this interface to access the MAC when the appropriate PLB address space is accessed.
Table 5-8: Tri-Mode Ethernet MAC Host Interface (Configuration/Status)
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Signal
rx_data[7:0]
rx_data_valid
rx_frame_good
rx_frame_bad
Signal
host_opcode[1:0]
host_addr[9:0]
host_wr_data[31:0]
host_rd_data_mac[31:0]
host_rd_data_stats[31:0]
host_miim_sel
host_req
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Direction
Input
Frame data received is supplied on this port.
Input
Control signal for the rx_data[7:0] port
Input
Asserted at the end of frame reception to indicate
that the frame should be processed by the
Ethernet AVB Endpoint core.
Input
Asserted at the end of frame reception to indicate
that the frame should be discarded by the MAC
client.
Table
Direction
Output
Defines the MAC operation
(configuration or MDIO, read or write)
Output
Address of the MAC register to access
Output
Data to be written to the MAC register
Input
Data read from the MAC register (connect
to the host_rd_data[31:0] signal of the
MAC)
Input
Data read from the Ethernet Statistics core
(connect to the host_rd_data[31:0] signal
of the Ethernet Statistics core, if present).
If the statistics core is not used, then
connect to logic 0.
Output
When asserted, the MAC will access the
MDIO port, when not asserted, the MAC
will access configuration registers
Output
Used to initiate a transaction onto the
MDIO
Core Interfaces
Description
"Standard CORE Generator
5-8) and are synchronous to
Description
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