Implement/Results; Component Name>/Simulation; Simulation/Functional - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

implement/results

The results directory is created by the implement script, after which the implement script
results are placed in the results directory.
Table 15-6: Results Directory
<component name>/simulation
The simulation directory and subdirectories that provide the files necessary to test a
Verilog or VHDL implementation of the example design. For more information, see
"Example Design," page
Table 15-7: Simulation Directory

simulation/functional

The functional directory contains functional simulation scripts provided with the core.
Table 15-8: Functional Directory
Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Name
<project_dir>/<component_name>/implement/results
routed.v[hd]
routed.sdf
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152.
Name
<project_dir>/<component_name>/simulation
demo_tb.v[hd]
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Name
<project_dir>/<component_name>/simulation/functional
simulate_mti.do
wave_mti.do
simulate_ncsim.sh
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Directory and File Contents
Description
Back-annotated SimPrim-based model used
for timing simulation.
Timing information for simulation.
Description
The demonstration test bench for the example
design. Instantiates the example design (the
Device Under Test (DUT)), generates clocks,
resets, and gathers statistics as the simulation
is run.
Description
ModelSim macro file that compiles Verilog or
VHDL sources and runs the functional
simulation to completion.
ModelSim macro file that opens a wave
window and adds signals of interest to it. It is
called by the
simulate_mti.do
IES script file that compiles the Verilog or
VHDL sources and runs the functional
simulation to completion.
macro file.
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