Implementation Scripts; Simulation Scripts; Functional Simulation - Xilinx LogiCORE IP Ethernet AVB Endpoint v2.4 User Manual

Implementation Scripts

The implementation script is either a shell script or batch file that processes the example
design through the Xilinx tool flow and is one of the following locations:
Linux
Windows
The implement script performs the following steps:
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The Xilinx tool flow generates several output and report files that are saved in the
following directory (which is created by the implement script):

Simulation Scripts

Functional Simulation

The test script is a ModelSim, IES, or VCS macro that automates the simulation of the test
bench and is in the following location:
The test script performs the following tasks:
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Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
<project_dir>/<component_name>/implement/implement.sh
<project_dir>/<component_name>/implement/implement.bat
HDL example design files are synthesized using XST.
Ngdbuild is run to consolidate the core netlist and the example design netlist into the
NGD file containing the entire design.
Design is mapped to the target technology.
Design is placed-and-routed on the target device.
Static timing analysis is performed on the routed design using
A bitstream is generated.
Netgen runs on the routed design to generate a VHDL or Verilog netlist (as
appropriate for the Design Entry project setting) and timing information in the form of
SDF files.
<project_dir>/<component_name>/implement/results
<project_dir>/<component_name>/simulation/functional/
Compiles the structural UniSim simulation model
Compiles HDL example design source code
Compiles the demonstration test bench
Starts a simulation of the test bench
Opens a Wave window and adds signals of interest
Runs the simulation to completion
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Implementation Scripts
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