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LogiCORE 1000BASE-X
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Manuals and User Guides for Xilinx LogiCORE 1000BASE-X. We have
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Xilinx LogiCORE 1000BASE-X manual available for free PDF download: User Manual
Xilinx LogiCORE 1000BASE-X User Manual (230 pages)
LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
Brand:
Xilinx
| Category:
Software
| Size: 3.18 MB
Table of Contents
Table of Contents
3
Revision History
2
Schedule of Figures
9
: the Ten-Bit Interface
10
Schedule of Tables
13
Preface: about this Guide
15
Guide Contents
15
Conventions
16
Typographical
16
Online Document
17
Chapter 1: Introduction
19
About the Core
19
Designs Using Rocketio Transceivers
19
Recommended Design Experience
19
Additional Core Resources
20
Related Xilinx Ethernet Products and Services
20
Specifications
20
Technical Support
20
Feedback
20
Ethernet 1000BASE-X PCS/PMA or SGMII Core
20
Document
21
Chapter 2: Core Architecture
23
System Overview
23
Ethernet 1000BASE-X PCS/PMA or SGMII Using a Rocketio Transceiver
23
Ethernet 1000BASE-X PCS/PMA or SGMII with Ten-Bit-Interface
25
Core Interfaces
26
Client Side Interface
31
Physical Side Interface
36
Chapter 3: Generating and Customizing the Core
39
GUI Interface
39
Component Name
39
Core Functionality
40
Select Standard
40
Sgmii/Dynamic Standard Switching Elastic Buffer Options
41
Rocketio Tile Configuration
43
Parameter Values in the XCO File
43
Output Generation
44
Chapter 4: Designing with the Core
45
Design Overview
45
Design Guidelines
50
Examine the Example Design Provided with the Core
50
Generate the Core
50
Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core
50
In Your Application
50
Chapter 5: Using the Client-Side GMII Data Path
53
Designing with the Client-Side GMII for the 1000BASE-X Standard
53
GMII Transmission
53
GMII Reception
54
Status_Vector[4:0] Signals
56
Using the Virtex-II Pro Rocketio Transceiver CRC Functionality
57
Designing with Client-Side GMII for the SGMII Standard
59
GMII Transmission
59
Overview
59
GMII Reception
60
Using the GMII as an Internal Connection
61
Implementing External GMII
61
GMII Transmitter Logic
61
GMII Receiver Logic
66
Chapter 6: The Ten-Bit Interface
69
Ten-Bit-Interface Logic
69
Transmitter Logic
69
Receiver Logic
70
Figure 6-2: Ten-Bit-Interface Receiver Logic
71
Clock Sharing Across Multiple Cores with TBI
77
Chapter 7: 1000BASE-X with Rocketio Transceivers
79
Rocketio Transceiver Logic
79
Virtex-II Pro Devices
79
Figure 7-1: 1000Base-X Connection to a Virtex-II Pro Mgt
80
Virtex-4 FX Devices
81
Figure 7-2: 1000Base-X Connection to Virtex-4 Mgt
82
Virtex-5 LXT and SXT Devices
83
Figure 7-3: 1000Base-X Connection to Virtex-5 Gtp Transceivers
84
Virtex-5 FXT Devices
85
Clock Sharing Across Multiple Cores with Rocketio
87
Virtex-II Pro Devices
87
Virtex-4 FX Devices
88
Figure 7-6: Clock Management - Multiple Core Instances, Mgts for 1000Base-X
89
Virtex-5 LXT and SXT Devices
90
Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 Rocketio Gtp
91
Transceivers
92
Virtex-5 FXT Devices
92
Transceivers
93
Figure 7-8: Clock Management - Multiple Core Instances, Virtex-5 Rocketio Gtx
93
Transceivers
94
Chapter 8: SGMII / Dynamic Standards Switching with Rocketio Transceivers
95
Receiver Elastic Buffer Implementations
95
Selecting the Buffer Implementation from the GUI
95
The Requirement for the FPGA Fabric Rx Elastic Buffer
96
The Rocketio Rx Elastic Buffer
97
Rocketio Logic Using the Rocketio Rx Elastic Buffer
98
Rocketio Logic with the Fabric Rx Elastic Buffer
98
Virtex-II Pro Devices
99
Figure 8-3: Sgmii Connection to a Virtex-II Pro Rocketio Transceiver
100
Virtex-4 Devices for SGMII or Dynamic Standards Switching
101
Figure 8-4: Sgmii Connection to a Virtex-4 Mgt
102
Virtex-5 LXT or SXT Devices for SGMII or Dynamic Standards Switching
103
Figure 8-5: Sgmii Connection to a Virtex-5 Rocketio Gtp Transceiver
104
Virtex-5 FXT Devices for SGMII or Dynamic Standards Switching
105
Figure 8-6: Sgmii Connection to a Virtex-5 Rocketio Gtx Transceiver
106
Clock Sharing - Multiple Cores with Rocketio, Fabric Elastic Buffer
107
Virtex-II Pro Devices
107
Figure 8-7: Clock Management with Multiple Core Instances with Virtex-II Pro
108
Virtex-4 FX Devices
109
Virtex-5 LXT and SXT Devices
111
Figure 8-9: Clock Management with Multiple Core Instances with Virtex-5 Gtp
112
Virtex-5 FXT Devices
113
Figure 8-10: Clock Management with Multiple Core Instances with Virtex-5 Gtx
114
Chapter 9: Configuration and Status
115
MDIO Management Interface
115
MDIO Bus System
115
MDIO Transactions
116
MDIO Addressing
117
Connecting the MDIO to an External STA
118
Connecting the MDIO to an Internally Integrated STA
118
Management Registers
119
1000BASE-X Standard Using the Optional Auto-Negotiation
119
1000BASE-X Standard Without the Optional Auto-Negotiation
129
SGMII Standard Using the Optional Auto-Negotiation
135
SGMII Standard Without the Optional Auto-Negotiation
145
Both 1000BASE-X and SGMII Standards
150
Optional Configuration Vector
151
Chapter 10: Auto-Negotiation
153
Overview of Operation
153
1000BASE-X Standard
153
SGMII Standard
155
Setting the Configurable Link Timer
156
1000BASE-X Standard
156
SGMII Standard
156
Simulating Auto-Negotiation
156
Using the Auto-Negotiation Interrupt
156
Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards
157
Typical Application
157
Operation of the Core
158
Auto-Negotiation State Machine
158
Selecting the Power-On / Reset Standard
158
Setting the Auto-Negotiation Link Timer
158
Switching the Standard Using MDIO
158
Chapter 12: Constraining the Core
161
Required Constraints
161
Device, Package, and Speedgrade Selection
161
I/O Location Constraints
161
Placement Constraints
161
Virtex-II Pro Rocketio Mgts for 1000BASE-X Constraints
161
Switching Constraints
163
Virtex-II Pro Rocketio Mgts for SGMII or Dynamic Standards
163
Virtex-4 Rocketio Mgts for 1000BASE-X Constraints
164
Virtex-4 Rocketio Mgts for SGMII or Dynamic Standards Switching Constraints
166
Virtex-5 Rocketio GTP Transceivers for 1000BASE-X Constraints
166
Switching Constraints
167
Virtex-5 Rocketio GTP Transceivers for SGMII or Dynamic Standards
167
Virtex-5 Rocketio GTX Transceivers for 1000BASE-X Constraints
167
Switching Constraints
168
Ten-Bit Interface Constraints
168
Virtex-5 Rocketio GTX Transceivers for SGMII or Dynamic Standards
168
Constraints When Implementing an External GMII
172
Understanding Timing Reports for Setup/Hold Timing
176
Chapter 13: Interfacing to Other Cores
179
Integrating with the 1-Gigabit Ethernet MAC Core
179
Integration of the 1-Gigabit Ethernet MAC to 1000BASE-X PCS with TBI
179
Integration of the 1-Gigabit Ethernet MAC Using a Rocketio Transceiver
181
(Or Dynamic Switching) Functionality
185
Integration of the 1-Gigabit Ethernet MAC to Provide SGMII
185
Integrating with the Tri-Mode Ethernet MAC Core
185
Integration of the Tri-Mode Ethernet MAC to Provide SGMII (or Dynamic Switching) Functionality with TBI
185
Integration of the Tri-Mode Ethernet MAC to Provide SGMII (or Dynamic Switching) Functionality Using Rocketio Transceivers
188
Chapter 14: Special Design Considerations
197
Power Management
197
Startup Sequencing
197
Loopback
197
Core with the TBI
197
Core with Rocketio Transceiver
198
Chapter 15: Implementing the Design
201
Pre-Implementation Simulation
201
Using the Simulation Model
201
Synthesis
201
Xst - Vhdl
201
XST - Verilog
202
Implementation
202
Generating the Xilinx Netlist
202
Mapping the Design
202
Placing and Routing the Design
202
Generating a Bitstream
203
Static Timing Analysis
203
Post-Implementation Simulation
203
Generating a Simulation Model
203
Using the Model
203
Other Implementation Information
204
Appendix A: Core Verification, Compliance, and Interoperability
205
Verification
205
Simulation
205
Hardware Verification
205
Appendix B: Core Latency
207
Core Latency
207
Latency for 1000BASE-X PCS with TBI
207
Latency for 1000BASE-X PCS and PMA Using a Rocketio Transceiver
208
Latency for SGMII
208
Appendix C: Calculating the DCM Fixed Phase Shift Value
209
Requirement for DCM Phase Shifting
209
Finding the Ideal Phase Shift Value for Your System
209
Appendix D: 1000BASE-X State Machines
211
Introduction
211
Start of Frame Encoding
212
The Even Transmission Case
212
Reception of the Even Case
213
The Odd Transmission Case
213
Reception of the Odd Case
214
Preamble Shrinkage
215
End of Frame Encoding
215
The Even Transmission Case
215
Reception of the Even Case
216
The Odd Transmission Case
216
Reception of the Odd Case
217
Appendix E: Rx Elastic Buffer Specifications
219
Introduction
219
Rx Elastic Buffers: Depths and Maximum Frame Sizes
219
Rocketio Rx Elastic Buffers
219
SGMII Fabric Rx Elastic Buffer
222
TBI Rx Elastic Buffer
223
Clock Correction
224
Maximum Frame Sizes for Sustained Frame Reception
226
Jumbo Frame Reception
226
Appendix F: Debugging Guide
227
General Checks
227
Problems with the MDIO
227
Problems with Data Reception or Transmission
227
Problems with Auto-Negotiation
228
Problems in Obtaining a Link (Auto-Negotiation Disabled)
228
Problems with a High Bit Error Rate
229
Debugging
229
Symptoms
229
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