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Getting Started
®
Figure 7.
Intel
Platform Controller Hub EG20T UART Port0 Connection Diagram in the
Carrier Board
D-Sub9pin
Connector (X19)
RS232C/RS485
DCD/GND
RXD/CTS+
TXD/RTS+
DTR/RXD+
GND/RXD-
DSR/CTS-
RTS/RTS-
CTS/TXD+
RI/TXD-
Note:
For the UART0 port, it is necessary to configure switches and jumpers for RS
transceiver selection. See
Caution:
Do not change the setting after powering on the system. Be careful to configure proper
setting if the intention is to change the setting. A fault in the setting could damage the
platform, the interconnecting cable, or the attached external device.
2
2.5.12
I
C*
The carrier board provides one I
the typical I
a multi-master bus. The Intel
pin header (X37) and 2x5 2.54mm pin header (X38) directly.
January 2012
Document Number: 324213-002
1
DGND
2
MHS442
(SW1)
3
4
DGND
5
6
MHS442
(SW2)
7
8
MHS121
(SW3)
9
Section 4.3.1
2
C* port from the Intel
2
C* bus specification. It operates as a master or slave device and supports
®
PCH EG20T I
®
Intel
Atom™ Processor E660 with Intel
MAX3245E
MAX3076E
RE
DE
MAX3076E
RE
DE
D33V
J16
DGND
for details.
®
PCH EG20T that conforms to
2
C* port is connected to the 1x4 2.54mm
®
Platform Controller Hub EG20T Development Kit
10pin-Header
D33V
(X46)
Intel® PCH
EG20T
DGND
DTR
J12
DCD
J13
DSR
J14
RI
J15
J17
RTS
J18
CTS
J19
TXD
J20
RXD
D33V
J21
DGND
User Manual
25
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