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Table 5.
Development Kit Feature Set Summary (Sheet 2 of 2)
Feature
PS/2 KB
1 port from SIO
PS/2 Mouse
1 port from SIO
Altera EPM570 MAXII system management
CPLD on the COM Express module and POST
CPLD
code display CPLD (Port 80h decode) on the
carrier board
7-segment LED
2 digits from CPLD
Buzzer
1
LPC
1 header (20-pin); for SIO and CPLD
®
Intel
TPM
1 header (20-pin)
Validation Header
1 header (40-pin)
GPIO
1 header (12-pin)
®
Intel
HD Audio
1 header (10-pin) from Audio Codec
7.1 Audio Jacks
1 port (Stereo Jack x 6) from Audio Codec
2
I
C*
1 header (4-pin) from PCH
SPI
1 header (10-pin) from PCH
CAN
1 header (4-pin) from PCH via CAN transceiver
JTAG Port
2 headers (PCH (6-pin), CPLD(14-pin))
DIP 8-pin socket x 1 to store SATA Option ROM
Serial ROM
& Ethernet MAC Address
Crystal Oscillator: 3
Clocks for PCH
CLK Buffer: 1 (for PCIe*)
CLK Generator: 1 (for SATA)
Push buttons
Power x 1, Reset x 1
8 layers, thickness: 63 mils (1.6mm), Halogen
PCB Specification
Free Multilayer Material
Operation: 0 to 40°C
Temperature
Storage: -20 to 85°C
Operation: 20 to 80%
Humidity
Storage: 5 to 95%
ATX connector x1
12V ATX connector x1
Power Supply
DC Jack: for AC Adapter (+12V, 5A)x1
CMOS Battery (CR2032) x1
Power management
ACPI Compliant
(ACPI)
®
Intel
Atom™ Processor E660 with Intel
User Manual
16
Board Implementation
®
Platform Controller Hub EG20T Development Kit
Comments
POST code display CPLD: Xilinx XC9572XL
From COM Express* connector
From COM Express* connector
From COM Express* connector
From COM Express* connector
From PCH
1 Realtek ALC888 CODEC
Transceiver: NXP TJA1040T
SPI EEPROM: Microchip 25LC512-I/P
SYSCLK: Osc (25MHz)
USBCLK: Osc (48MHz)
UARTCLK: Osc (1.8432MHz)
SATACLK: CLK Gen (75MHz)
PCIeCLK: CLK Buff (100MHz)
All components are RoHS compliant
Power indicated LED and header
S0 – Power On
S3 – Suspend to RAM
(S4 – Suspend to Disk)
S5 – Soft Off
Document Number: 324213-002
Getting Started
January 2012
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