Epson S1C63000 Core Cpu Manual page 35

0
CLK
PK
PL
PC
pc-2 pc-1
ANY ANY
FETCH
BS16
DBS1/0
ANY
WR
RD
RDIV
DA00–DA15
ANY
D0–D3
M00–M15
IRQ
IACK
NACK
IF
Interrupt sampling
0
CLK
PK
PL
PC pc-3 pc-2
ANY LDB %EXT,imm8
FETCH
BS16
DBS1/0 ANY
WR
RD
RDIV
DA00–DA15
D0–D3
M00–M15
IRQ
IACK
NACK
IF
Interrupt sampling
S1C63000 CORE CPU MANUAL
1 2 3
pc
DUMMY
2 1
SP2-1 DUMMY
F reg. xH
Inte rrupt vector
Interrupt processing by the hardware Executing the interrupt service routine
4–6 cycle
1 2
pc-1 pc
LD %A,[%X] DUMMY
0 3 2
ANY 00xxH SP2-1
[00xxH] F reg.
Interrupt processing by the hardware Executing the interrupt service routine
4 5
010xH ANY
(010xH) ANY
2 ANY
SP1-1
pc
3 4 5
010xH ANY
(010xH) ANY
1 2 ANY
DUMMY SP1-1
xH
Inte rrupt vector
pc
EPSON
CHAPTER 3: CPU OPERATION
Fig. 3.5.2.3 Hardware interrupt
(IRQ) sequence
(normal acceptance)
In this chart, the dummy fetch
cycle starts after fetching the
"LD %A, [%X]" instruction
that follows the "LDB %EXT,
imm8" instruction.
Fig. 3.5.2.4 Hardware interrupt
(IRQ) sequence
(interrupt acceptance
after 1 instruction)
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