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Mnemonic
12
INC
[%X],n4
[%X]+,n4
[%Y],n4
[%Y]+,n4
[00addr6]
INT
imm6
JP
%Y
JR
%A
%BA
sign8
[00addr6]
JRC
sign8
JRNC
sign8
JRNZ
sign8
JRZ
sign8
LD
%A,%A
%A,%B
%A,%F
%A,imm4
%A,[%X]
%A,[%X]+
%A,[%Y]
%A,[%Y]+
%B,%A
%B,%B
%B,imm4
%B,[%X]
%B,[%X]+
%B,[%Y]
%B,[%Y]+
%F,%A
%F,imm4
[%X],%A
[%X],%B
[%X],imm4
[%X],[%Y]
[%X],[%Y]+
[%X]+,%A
[%X]+,%B
[%X]+,imm4
[%X]+,[%Y]
[%X]+,[%Y]+
[%Y],%A
[%Y],%B
[%Y],imm4
[%Y],[%X]
[%Y],[%X]+
[%Y]+,%A
[%Y]+,%B
[%Y]+,imm4
[%Y]+,[%X]
[%Y]+,[%X]+
LDB
%BA,%EXT
%BA,%SP1
%BA,%SP2
%BA,%XH
%BA,%XL
S1C63000 CORE CPU MANUAL
Machine code
11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 0 0 [ 10H-n4 ]
1 1 1 0 1 1 0 0 1 [ 10H-n4 ]
1 1 1 0 1 1 0 1 0 [ 10H-n4 ]
1 1 1 0 1 1 0 1 1 [ 10H-n4 ]
1 0 0 0 0 0 1 a5 a4 a3 a2 a1 a0
1 1 1 1 1 1 0 i5 i4 i3 i2 i1 i0
1 1 1 1 1 1 1 1 1 0 0 1 X
1 1 1 1 1 1 1 1 1 0 0 0 1
1 1 1 1 1 1 1 1 1 0 0 0 0
0 0 0 0 0 s7 s6 s5 s4 s3 s2 s1 s0
1 1 1 1 1 0 1 a5 a4 a3 a2 a1 a0
0 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0
0 0 1 0 1 s7 s6 s5 s4 s3 s2 s1 s0
0 0 1 1 1 s7 s6 s5 s4 s3 s2 s1 s0
0 0 1 1 0 s7 s6 s5 s4 s3 s2 s1 s0
1 1 1 1 0 1 1 1 1 0 0 0 0
1 1 1 1 0 1 1 1 1 0 0 1 0
1 1 1 1 1 1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0 0 i3 i2 i1 i0
1 1 1 1 0 1 1 1 0 0 0 0 0
1 1 1 1 0 1 1 1 0 0 0 0 1
1 1 1 1 0 1 1 1 0 0 0 1 0
1 1 1 1 0 1 1 1 0 0 0 1 1
1 1 1 1 0 1 1 1 1 0 1 0 0
1 1 1 1 0 1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0 1 i3 i2 i1 i0
1 1 1 1 0 1 1 1 0 0 1 0 0
1 1 1 1 0 1 1 1 0 0 1 0 1
1 1 1 1 0 1 1 1 0 0 1 1 0
1 1 1 1 0 1 1 1 0 0 1 1 1
1 1 1 1 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 i3 i2 i1 i0
1 1 1 1 0 1 1 1 0 1 0 0 0
1 1 1 1 0 1 1 1 0 1 1 0 0
1 1 1 1 0 1 0 0 0 i3 i2 i1 i0
1 1 1 1 0 1 1 1 1 1 0 1 0
1 1 1 1 0 1 1 1 1 1 0 1 1
1 1 1 1 0 1 1 1 0 1 0 0 1
1 1 1 1 0 1 1 1 0 1 1 0 1
1 1 1 1 0 1 0 0 1 i3 i2 i1 i0
1 1 1 1 0 1 1 1 1 1 1 1 0
1 1 1 1 0 1 1 1 1 1 1 1 1
1 1 1 1 0 1 1 1 0 1 0 1 0
1 1 1 1 0 1 1 1 0 1 1 1 0
1 1 1 1 0 1 0 1 0 i3 i2 i1 i0
1 1 1 1 0 1 1 1 1 1 0 0 0
1 1 1 1 0 1 1 1 1 1 0 0 1
1 1 1 1 0 1 1 1 0 1 0 1 1
1 1 1 1 0 1 1 1 0 1 1 1 1
1 1 1 1 0 1 0 1 1 i3 i2 i1 i0
1 1 1 1 0 1 1 1 1 1 1 0 0
1 1 1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 0 1 0 1 1 X
1 1 1 1 1 1 1 0 0 1 1 0 X
1 1 1 1 1 1 1 0 0 1 1 1 X
1 1 1 1 1 1 1 0 0 1 0 0 1
1 1 1 1 1 1 1 0 0 1 0 0 0
Operation
[X]
N's adjust ([X]+1)
[X]
N's adjust ([X]+1), X
X+1
[Y]
N's adjust ([Y]+1)
[Y]
N's adjust ([Y]+1), Y
Y+1
[00addr6]
[00addr6]+1
[SP2-1]
F, SP2
SP2-1
([(SP1-1) 4+3]~[(SP1-1) 4])
SP1
SP1-1, PC
imm6 (imm6=0100H~013FH)
PC
Y
PC
PC+A+1
PC
PC+BA+1
PC
PC+sign8+1 (sign8=-128~127)
PC
PC+[00addr6]+1
If C=1 then PC
PC+sign8+1 (sign8=-128~127)
If C=0 then PC
PC+sign8+1 (sign8=-128~127)
If Z=0 then PC
PC+sign8+1 (sign8=-128~127)
If Z=1 then PC
PC+sign8+1 (sign8=-128~127)
A
A
A
B
A
F
A
imm4
A
[X]
A
[X], X
X+1
A
[Y]
A
[Y], Y
Y+1
B
A
B
B
B
imm4
B
[X]
B
[X], X
X+1
B
[Y]
B
[Y], Y
Y+1
F
A
F
imm4
[X]
A
[X]
B
[X]
imm4
[X]
[Y]
[X]
[Y], Y
Y+1
[X]
A, X
X+1
[X]
B, X
X+1
[X]
imm4, X
X+1
[X]
[Y], X
X+1
[X]
[Y], X
X+1, Y
Y+1
[Y]
A
[Y]
B
[Y]
imm4
[Y]
[X]
[Y]
[X], X
X+1
[Y]
A, Y
Y+1
[Y]
B, Y
Y+1
[Y]
imm4, Y
Y+1
[Y]
[X], Y
Y+1
[Y]
[X], Y
Y+1, X
X+1
BA
EXT
BA
SP1
BA
SP2
BA
XH
BA
XL
EPSON
CHAPTER 4: INSTRUCTION SET
Flag
Cycle
E I C Z
2
–
2
–
2
–
2
–
2
–
3
– – –
PC+1,
1
– – –
1
– – –
1
– – –
1
– – –
2
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
1
1
– – –
1
– – –
1
– – –
2
– – –
2
– – –
1
– – –
1
– – –
1
– – –
2
– – –
2
– – –
1
– – –
1
– – –
1
– – –
2
– – –
2
– – –
1
– – –
1
– – –
1
– – –
2
– – –
2
– – –
1
– – –
1
– – –
1
– – –
1
– – –
1
– – –
EXT.
Page
mode
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