Flags - Epson S1C63000 Core Cpu Manual

• A and B registers
The A and B registers are respective 4-bit data registers that are used for data transfer and operation
with other registers, data memories or immediate data. They are used independently for 4-bit trans-
fer/operations and used in a BA pair that makes the B register the high-order 4 bits for 8-bit transfer/
operations.
• X and Y registers
The X and Y registers are respective 16-bit index registers that are used for indirect addressing of the
data memory. These registers are configured as an 8-bit register pair (high-order 8 bits: XH/YH, low-
order 8 bits: XL/YL) and data transfer/operations can be done in an 8-bit unit or a 16-bit unit.
• PC (program counter)
The PC is a 16-bit counter to address a program memory and indicates the following address to be
executed.
• SP1 and SP2 (stack pointers)
The SP1 and SP2 are respective 8-bit registers that indicate a stack address in the data memory. 8 bits
of the SP1 correspond to the DA02 to DA09 bits of the address bus for 16-bit data accessing (address
stacking) and it is used to operate the stack in a 4-word (16-bit) unit. 8 bits of the SP2 correspond to
the low-order 8 bits (DA01 to DA07) of the address bus for 4-bit data accessing and it is used to
operate stack in 1-word (4-bit) unit.
See Section 2.3.3, "Stack and stack pointer" for details of the stack operation.
• EXT register
The EXT register is an 8-bit data register that is used when an address or data is extended into 16 bits.
See Section 2.1.5, "EXT register and data extension", for details.
• F register
The F register includes 4 bits of flags; Z and C flags that are changed by operation results, I flag that is
used to enable/disable interrupts, and E flag that indicates extended addressing mode.
• Queue register
The queue register is used as a queue buffer for data when the SP1 processes 16-bit stack operations.
This register is provided in order to process 16-bit data pop operations from the SP1 stack at high-
speed. The queue register is accessed by the hardware, so it is not necessary to be aware of the register
operation when programming.

2.1.3 Flags

The S1C63000 contains a 4-bit flag register (F register) that indicates such things as the operation result
status within the CPU.
• Z (zero) flag
The Z flag is set to "1" when the execution result of an arithmetic instruction or a shift/rotate instruc-
tion has become "0" and is reset to "0'" when the result is other than "0".
Arithmetic instructions that change the Z flag:
ADD, ADC, SUB, SBC, CMP, INC, DEC, AND, OR, XOR, BIT, CLR, SET, TST
S1C63000 CORE CPU MANUAL
F
3 0
Flag register
E I C Z
Z (zero) flag
C (carry) flag
I (interrupt) flag
E (extension mode) flag
Fig. 2.1.3.1 F (flag) register
EPSON
CHAPTER 2: ARCHITECTURE
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