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CHAPTER 4: INSTRUCTION SET
Mnemonic
12
SLL
[%X]
1 0 0 0 0 1 1 1 0 0 0 0 0
[%X]+
1 0 0 0 0 1 1 1 0 0 0 0 1
[%Y]
1 0 0 0 0 1 1 1 0 0 0 1 0
[%Y]+
1 0 0 0 0 1 1 1 0 0 0 1 1
SLP
1 1 1 1 1 1 1 1 1 1 1 0 1
SRL
%A
1 0 0 0 0 1 1 1 1 0 0 0 1
%B
1 0 0 0 0 1 1 1 1 0 1 0 1
[%X]
1 0 0 0 0 1 1 1 0 0 1 0 0
[%X]+
1 0 0 0 0 1 1 1 0 0 1 0 1
[%Y]
1 0 0 0 0 1 1 1 0 0 1 1 0
[%Y]+
1 0 0 0 0 1 1 1 0 0 1 1 1
SUB
%A,%A
1 1 0 0 0 0 1 1 1 0 0 0 X
%A,%B
1 1 0 0 0 0 1 1 1 0 0 1 X
%A,imm4
1 1 0 0 0 0 1 0 0 i3 i2 i1 i0
%A,[%X]
1 1 0 0 0 0 1 1 0 0 0 0 0
%A,[%X]+
1 1 0 0 0 0 1 1 0 0 0 0 1
%A,[%Y]
1 1 0 0 0 0 1 1 0 0 0 1 0
%A,[%Y]+
1 1 0 0 0 0 1 1 0 0 0 1 1
%B,%A
1 1 0 0 0 0 1 1 1 0 1 0 X
%B,%B
1 1 0 0 0 0 1 1 1 0 1 1 X
%B,imm4
1 1 0 0 0 0 1 0 1 i3 i2 i1 i0
%B,[%X]
1 1 0 0 0 0 1 1 0 0 1 0 0
%B,[%X]+
1 1 0 0 0 0 1 1 0 0 1 0 1
%B,[%Y]
1 1 0 0 0 0 1 1 0 0 1 1 0
%B,[%Y]+
1 1 0 0 0 0 1 1 0 0 1 1 1
[%X],%A
1 1 0 0 0 0 1 1 0 1 0 0 0
[%X],%B
1 1 0 0 0 0 1 1 0 1 1 0 0
[%X],imm4
1 1 0 0 0 0 0 0 0 i3 i2 i1 i0
[%X]+,%A
1 1 0 0 0 0 1 1 0 1 0 0 1
[%X]+,%B
1 1 0 0 0 0 1 1 0 1 1 0 1
[%X]+,imm4
1 1 0 0 0 0 0 0 1 i3 i2 i1 i0
[%Y],%A
1 1 0 0 0 0 1 1 0 1 0 1 0
[%Y],%B
1 1 0 0 0 0 1 1 0 1 1 1 0
[%Y],imm4
1 1 0 0 0 0 0 1 0 i3 i2 i1 i0
[%Y]+,%A
1 1 0 0 0 0 1 1 0 1 0 1 1
[%Y]+,%B
1 1 0 0 0 0 1 1 0 1 1 1 1
[%Y]+,imm4
1 1 0 0 0 0 0 1 1 i3 i2 i1 i0
TST
[00addr6],imm2
1 0 0 1 0 i1 i0 a5 a4 a3 a2 a1 a0
1 0 0 1 1 i1 i0 a5 a4 a3 a2 a1 a0
[FFaddr6],imm2
XOR
%A,%A
1 1 0 1 1 1 1 1 1 0 0 0 X
%A,%B
1 1 0 1 1 1 1 1 1 0 0 1 X
%A,imm4
1 1 0 1 1 1 1 0 0 i3 i2 i1 i0
%A,[%X]
1 1 0 1 1 1 1 1 0 0 0 0 0
%A,[%X]+
1 1 0 1 1 1 1 1 0 0 0 0 1
%A,[%Y]
1 1 0 1 1 1 1 1 0 0 0 1 0
%A,[%Y]+
1 1 0 1 1 1 1 1 0 0 0 1 1
%B,%A
1 1 0 1 1 1 1 1 1 0 1 0 X
%B,%B
1 1 0 1 1 1 1 1 1 0 1 1 X
%B,imm4
1 1 0 1 1 1 1 0 1 i3 i2 i1 i0
%B,[%X]
1 1 0 1 1 1 1 1 0 0 1 0 0
%B,[%X]+
1 1 0 1 1 1 1 1 0 0 1 0 1
%B,[%Y]
1 1 0 1 1 1 1 1 0 0 1 1 0
%B,[%Y]+
1 1 0 1 1 1 1 1 0 0 1 1 1
%F,imm4
1 0 0 0 0 1 0 1 0 i3 i2 i1 i0
[%X],%A
1 1 0 1 1 1 1 1 0 1 0 0 0
[%X],%B
1 1 0 1 1 1 1 1 0 1 1 0 0
[%X],imm4
1 1 0 1 1 1 0 0 0 i3 i2 i1 i0
[%X]+,%A
1 1 0 1 1 1 1 1 0 1 0 0 1
[%X]+,%B
1 1 0 1 1 1 1 1 0 1 1 0 1
[%X]+,imm4
1 1 0 1 1 1 0 0 1 i3 i2 i1 i0
[%Y],%A
1 1 0 1 1 1 1 1 0 1 0 1 0
[%Y],%B
1 1 0 1 1 1 1 1 0 1 1 1 0
[%Y],imm4
1 1 0 1 1 1 0 1 0 i3 i2 i1 i0
[%Y]+,%A
1 1 0 1 1 1 1 1 0 1 0 1 1
[%Y]+,%B
1 1 0 1 1 1 1 1 0 1 1 1 1
[%Y]+,imm4
1 1 0 1 1 1 0 1 1 i3 i2 i1 i0
54
Machine code
11 10 9 8 7 6 5 4 3 2 1 0
Operation
[X] (C D3 D2 D1 D0 0)
[X] (C D3 D2 D1 D0 0), X
[Y] (C D3 D2 D1 D0 0)
[Y] (C D3 D2 D1 D0 0), Y
Sleep
A (0 D3 D2 D1 D0 C)
B (0 D3 D2 D1 D0 C)
[X] (0 D3 D2 D1 D0 C)
[X] (0 D3 D2 D1 D0 C), X
[Y] (0 D3 D2 D1 D0 C)
[Y] (0 D3 D2 D1 D0 C), Y
A
A-A
A
A-B
A
A-imm4
A
A-[X]
A
A-[X], X
X+1
A
A-[Y]
A
A-[Y], Y
Y+1
B
B-A
B
B-B
B
B-imm4
B
B-[X]
B
B-[X], X
X+1
B
B-[Y]
B
B-[Y], Y
Y+1
[X]
[X]-A
[X]
[X]-B
[X]
[X]-imm4
[X]
[X]-A, X
X+1
[X]
[X]-B, X
X+1
[X]
[X]-imm4, X
X+1
[Y]
[Y]-A
[Y]
[Y]-B
[Y]
[Y]-imm4
[Y]
[Y]-A, Y
Y+1
[Y]
[Y]-B, Y
Y+1
[Y]
[Y]-imm4, Y
Y+1
[00addr6] (2
imm2
)
[FFaddr6] (2
)
imm2
A
A A
A
A B
A
A imm4
A
A [X]
A
A [X], X
X+1
A
A [Y]
A
A [Y], Y
Y+1
B
B A
B
B B
B
B imm4
B
B [X]
B
B [X], X
X+1
B
B [Y]
B
B [Y], Y
Y+1
F
F imm4
[X]
[X] A
[X]
[X] B
[X]
[X] imm4
[X]
[X] A, X
X+1
[X]
[X] B, X
X+1
[X]
[X] imm4, X
X+1
[Y]
[Y] A
[Y]
[Y] B
[Y]
[Y] imm4
[Y]
[Y] A, Y
Y+1
[Y]
[Y] B, Y
Y+1
[Y]
[Y] imm4, Y
Y+1
EPSON
Flag
EXT.
Cycle
E I C Z
mode
2
–
X+1
2
–
2
–
Y+1
2
–
2
– – –
1
–
1
–
2
–
X+1
2
–
2
–
Y+1
2
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
2
–
2
–
2
–
2
–
2
–
2
–
2
–
2
–
2
–
2
–
2
–
2
–
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
– –
1
2
– –
2
– –
2
– –
2
– –
2
– –
2
– –
2
– –
2
– –
2
– –
2
– –
2
– –
2
– –
S1C63000 CORE CPU MANUAL
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