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CHAPTER 3: CPU OPERATION
After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1 and
SP2 are set by software.
3.4.2 Initial setting of internal registers
An initial reset initializes the internal registers in the CPU as shown in Table 3.4.2.1.
The registers and flags which are not initialized at an initial reset should be initialized in the program if
necessary.
Be sure to set both the stack pointers SP1 and SP2. All the interrupts cannot be accepted if they are not set
as a pair.
3.5 Interrupts
Interrupt is a function to process factors, that generate asynchronously with program execution, such as a
key entry and an end of a peripheral circuit operation. When the CPU accepts an interrupt request that is
sent by the hardware, the CPU stops executing the current sequence of the program and shifts into the
interrupt processing. When all the interrupt processing has finished, the interrupted program is resumed.
The S1C63000 has the hardware interrupt function for the peripheral circuits including an NMI (non-
maskable interrupt) and the hardware interrupt function. The hardware interrupts excluding the NMI
can be set to the DI (disable interrupts) status by setting the I (interrupt) flag.
I flag = "1": EI (enable interrupts) status
I flag = "0": DI (disable interrupts) status ...The CPU does not accept interrupt requests from the periph-
The I flag is set to "0" at an initial reset. Furthermore, all the interrupts including NMI are masked and
cannot be accepted regardless of the I flag setting until both the stack pointers SP1 and SP2 are set in the
program after an initial reset.
3.5.1 Interrupt vectors
Interrupt vectors are provided to execute a interrupt service routine corresponding to the interrupt
generated.
The interrupt vectors are assigned to the following addresses in the ROM.
NMI interrupt vector:
Hardware interrupt vectors:
Software interrupt vectors:
26
Table 3.4.2.1 Initial setting of internal registers
Name
Data register A
Data register B
Extension register EXT
Index register X
Index register Y
Program counter
Stack pointer SP1
Stack pointer SP2
Zero flag
Carry flag
Interrupt flag
Extension flag
Queue register
...The CPU accepts interrupt requests from the peripheral
circuits.
eral circuits. (excluding NMI and software interrupts)
0100H
0101H to 010FH
0111H to 013FH
Symbol
Number of bits
Setting value
A
4
B
4
EXT
8
X
16
Y
16
PC
16
SP1
8
SP2
8
Z
1
C
1
I
1
E
1
Q
16
EPSON
Undefined
Undefined
Undefined
Undefined
Undefined
0110H
Undefined
Undefined
Undefined
Undefined
0
0
Undefined
S1C63000 CORE CPU MANUAL
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