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16-bit immediate data addressing
Mnemonic
LDB
%EXT,imm8 1
LDB
%XL,imm8 2
LDB
%EXT,imm8 1
LDB
%YL,imm8 2
LDB
%EXT,imm8 1
ADD
%X,sign8 2
LDB
%EXT,imm8 1
ADD
%Y,sign8 2
LDB
%EXT,imm8 1
CMP
%X,imm8 2
LDB
%EXT,imm8 1
CMP
%X,imm8 2
signed 16-bit PC relative addressing
Mnemonic
LDB
%EXT,imm8
JR
sign8
LDB
%EXT,imm8
JRC
sign8
LDB
%EXT,imm8
JRNC
sign8
LDB
%EXT,imm8
JRZ
sign8
LDB
%EXT,imm8
JRNZ
sign8
LDB
%EXT,imm8
CALR
sign8
4.3 Instruction Formats
All the instructions of the S1C63000 are configured with 1 word (13 bits) as follows:
I
13-bit operation code
9-bit operation code + 4-bit immediate data
II
7-bit operation code + 6-bit immediate data
III
OP Code
5-bit operation code + 8-bit immediate data
IV
OP Code
5-bit operation code + 2-bit immediate data + 6-bit immediate data
V
OP Code
S1C63000 CORE CPU MANUAL
X
imm16 ( 1 is upper 8-bit, 2 is lower 8-bit)
Y
imm16 ( 1 is upper 8-bit, 2 is lower 8-bit)
X
X + imm16 ( 1 is upper 8-bit, 2 is lower 8-bit)
Y
Y + imm16 ( 1 is upper 8-bit, 2 is lower 8-bit)
X - imm16 (FFH - 1 is upper 8-bit, 2 is lower 8-bit)
Y - imm16 (FFH - 1 is upper 8-bit, 2 is lower 8-bit)
(sign16 : imm8 is upper 8-bit, sign8 is lower 8-bit)
PC
PC + sign16 + 1 (sign16 = 32767~-32768)
If C = 1 then PC
PC + sign16 + 1 (sign16 = 32767 ~ -32768)
If C = 0 then PC
PC + sign16 + 1 (sign16 = 32767 ~ -32768)
If Z = 1 then PC
PC + sign16 + 1 (sign16 = 32767 ~ -32768)
If Z = 0 then PC
PC + sign16 + 1 (sign16 = 32767 ~ -32768)
( [SP1 - 1 4 + 3] ~ [ (SP1 - 1) 4] )
PC
PC + sign16 + 1 (sign16 = 32767 ~ -32768)
OP Code
OP Code
Operand
Operand
Operation
Operation
PC + 1, SP1
Examples:
Examples:
Operand
Examples:
Operand
Examples:
Examples:
Operand
EPSON
CHAPTER 4: INSTRUCTION SET
E I C Z
E I C Z
SP1 - 1
LD
%A,%B
ADD
%A,[%X]
PUSH
%F
LD
%A,imm4
ADC
[%Y],%B,n4
BIT
%B,imm4
INC
[addr6]
CALR
[addr6]
INT
imm6
LDB
%BA,imm8
CALZ
imm8
JR
sign8
CLR
[addr6],imm2
SET
[addr6],imm2
TST
[addr6],imm2
Flag
– – –
– – –
– –
– –
–
–
Flag
– – –
– – –
– – –
– – –
– – –
– – –
59
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