Epson S1C63000 Core Cpu Manual page 87

BIT [%ir],imm4
Function: [ir] imm4
Performs a logical AND of the 4-bit immediate data imm4 and the content of the data memory
addressed by the ir register (X or Y) to check the bits of the memory. The Z flag is changed due
to the operation result, but the content of the memory is not changed.
Code:
Mnemonic
BIT [%X],imm4
BIT [%Y],imm4
E I
Flags:
–
Src: Immediate data
Mode:
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: BIT [%X],imm4
LDB %EXT,imm8
BIT [%Y],imm4
BIT [%ir]+,imm4
Function: [ir] imm4, ir
Performs a logical AND of the 4-bit immediate data imm4 and the content of the data memory
addressed by the ir register (X or Y) to check the bits of the memory. The Z flag is changed due
to the operation result, but the content of the memory is not changed. Then increments the ir
register (X or Y). The increment result of the ir register does not affect the flags.
Code:
Mnemonic
BIT [%X]+,imm4
BIT [%Y]+,imm4
E I
Flags:
–
Src: Immediate data
Mode:
Dst: Register indirect
Extended addressing: Invalid
S1C63000 CORE CPU MANUAL
Test bit of location [ir reg.] with immediate data imm4
MSB
1 1 0 1 0 1 0 0 0 i3 i2 i1 i0 1A80H–1A8FH
1 1 0 1 0 1 0 1 0 i3 i2 i1 i0 1AA0H–1AAFH
C Z
–
[00imm8] imm4 (00imm8 = 0000H + 00H to FFH)
[FFimm8] imm4 (FFimm8 = FF00H + 00H to FFH)
Test bit of location [ir reg.] with immediate data imm4 and increment ir reg. 1 cycle
ir + 1
MSB
1 1 0 1 0 1 0 0 1 i3 i2 i1 i0 1A90H–1A9FH
1 1 0 1 0 1 0 1 1 i3 i2 i1 i0 1AB0H–1ABFH
C Z
–
EPSON
CHAPTER 4: INSTRUCTION SET
LSB
LSB
1 cycle
81