Interrupt Sequence - Epson S1C63000 Core Cpu Manual

Each of the addresses listed above corresponds to an interrupt factor individually. A branch (jump)
instruction to the interrupt service routine should be written to these addresses.
Up to 15 hardware interrupt vectors are available, however, the number of vectors is different depending
on the S1C63 Family models. The addresses, that are not assigned to the hardware interrupt vector within
the addresses 0101H to 010FH, can be used as software interrupt vectors. In addition, since the hardware
interrupt service routines can be executed using the software interrupt, up to 63 software interrupts can
be used (excluding the address 0110H because it is the program start address).

3.5.2 Interrupt sequence

• Hardware interrupts
Hardware interrupts including NMI are generated by the peripheral circuits. The peripheral circuit
that contains the interrupt function outputs an interrupt request to the CPU when the interrupt factor
is generated. The NMI terminal for NMI or IRQ terminal for other interrupts goes low. Sampling the
NMI signal is done at the falling edge by the CPU. Sampling the IRQ signal is done at the rising edge
of the T3 state in the bus cycle. The CPU executes the following process after accepting an interrupt
request.
Bus cycle 0 Sampling the interrupt request.
Bus cycle 1 The last execution cycle of the instruction under execution becomes a dummy fetch
cycle. This cycle turns the interrupt acknowledge signal low (both NACK and IACK for
NMI, IACK only for a normal interrupt), which indicates that the interrupt has been
accepted.
Bus cycle 2 Saves the F register into the stack indicated by the SP2, then resets the I flag to "0" to
prohibit following interrupts (excluding NMI).
Bus cycle 3 Sets the data bus status DBS1/DBS0 to "01B". Then, turns the vector read signal RDIV
low and reads the interrupt vector (4 bits) output from the peripheral circuit to the data
bus.
When NMI is generated, this cycle becomes a dummy cycle because the interrupt vector
is fixed at 0100H.
The NACK and/or IACK are returned to high at the end of this cycle.
Bus cycle 4 Fetches the instruction in the interrupt vector (data that is read in Bus cycle 3 becomes
the low-order 4 bits of the vector) and saves the content of the PC (address immediately
after the instruction that is executed in Bus cycle 0 or branch destination address when
it is a branch instruction) to the stack indicated by the SP1.
Bus cycle 5 Executes the instruction fetched in Bus cycle 4. (If it is 1-cycle instruction, the next
instruction is fetched at the same time.)
• Exceptional acceptance of interrupt
For all the interrupts including NMI that are generated during fetching the following instructions
are accepted after the next instruction is fetched (it is executed) even in the EI (enable interrupts)
status.
1. Instructions that set the E flag
LDB %EXT,imm8
2. Instructions that write data in the F (flag) register
LD %F,%A
XOR %F,imm4
These instructions set the E flag or may set it. Therefore, if an extended addressing instruction
follows them, it is executed previous to the interrupt processing.
Further, these instructions may modify the content of the I flag. If these instructions set the I flag
(EI status), the interrupt processing is done after executing the next instruction. If these instruc-
tions reset the I flag (DI status), interrupts generated after the instruction fetch cycle are masked.
S1C63000 CORE CPU MANUAL
LDB %EXT,%BA
LD %F,imm4 AND %F,imm4
POP %F RETI
EPSON
CHAPTER 3: CPU OPERATION
OR %F,imm4
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