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CHAPTER 4: INSTRUCTION SET
SRL [%ir]
Function:
0
3 2 1 0
Shifts the content of the data memory addressed by the ir register (X or Y) to the right for 1 bit.
Bit 0 of the r register moves to the C flag and bit 3 goes "0".
Code:
Mnemonic
SRL [%X]
SRL [%Y]
Flags:
E
I
–
Register indirect
Mode:
Extended addressing: Valid
Extended LDB
%EXT,imm8
operation: SRL
[%X]
LDB
%EXT,imm8
SRL
[%Y]
SRL [%ir]+
Function:
0
3 2 1 0
Shifts the content of the data memory addressed by the ir register (X or Y) to the right for 1 bit.
Bit 0 of the r register moves to the C flag and bit 3 goes "0". Then increments the ir register (X
or Y). The increment result of the ir register does not affect the flags.
Code:
Mnemonic
SRL [%X]+
SRL [%Y]+
Flags:
E
I
–
Register indirect
Mode:
Extended addressing: Invalid
134
Shift right location [ir reg.] logical
C
[ir]
MSB
1 0 0 0 0 1 1 1 0 0 1 0 0
1 0 0 0 0 1 1 1 0 0 1 1 0
C
Z
Shifts the content of [00imm8] (00imm8 = 0000H + 00H to FFH)
Shifts the content of [FFimm8] (FFimm8 = FF00H + 00H to FFH)
Shift right location [ir reg.] logical and increment ir reg.
, ir
ir + 1
C
[ir]
MSB
1 0 0 0 0 1 1 1 0 0 1 0 1
1 0 0 0 0 1 1 1 0 0 1 1 1
C
Z
EPSON
LSB
10E4H
10E6H
LSB
10E5H
10E7H
S1C63000 CORE CPU MANUAL
2 cycles
2 cycles
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