Xor [%Ir]+,Imm - Epson S1C63000 Core Cpu Manual

XOR [%ir],imm4
Function: [ir] [ir]
Performs an exclusive OR operation of the 4-bit immediate data imm4 and the content of the
data memory addressed by the ir register (X or Y), and stores the result in that address.
Code:
Mnemonic
XOR [%X],imm4
XOR [%Y],imm4
Flags: E I
–
Src: Immediate data
Mode:
Dst: Register indirect
Extended addressing: Valid
Extended LDB %EXT,imm8
operation: XOR [%X],imm4
LDB %EXT,imm8
XOR [%Y],imm4

XOR [%ir]+,imm4

Function: [ir] [ir]
Performs an exclusive OR operation of the 4-bit immediate data imm4 and the content of the
data memory addressed by the ir register (X or Y), and stores the result in that address. Then
increments the ir register (X or Y). The flags change due to the operation result of the data
memory and the increment result of the ir register does not affect the flags.
Code:
Mnemonic
XOR [%X]+,imm4
XOR [%Y]+,imm4
E I
Flags:
–
Src: Immediate data
Mode:
Dst: Register indirect
Extended addressing: Invalid
S1C63000 CORE CPU MANUAL
Exclusive OR immediate data imm4 and location [ir reg.]
imm4
MSB
1 1 0 1 1 1 0 0 0 i3 i2 i1 i0 1B80H–1B8FH
1 1 0 1 1 1 0 1 0 i3 i2 i1 i0 1BA0H–1BAFH
C Z
–
[00imm8]
[FFimm8]
Exclusive OR immediate data imm4 and location [ir reg.] and increment ir reg. 2 cycles
imm4, ir ir + 1
MSB
1 1 0 1 1 1 0 0 1 i3 i2 i1 i0 1B90H–1B9FH
1 1 0 1 1 1 0 1 1 i3 i2 i1 i0 1BB0H–1BBFH
C Z
–
[00imm8] imm4 (00imm8 = 0000H + 00H to FFH)
[FFimm8] imm4 (FFimm8 = FF00H + 00H to FFH)
EPSON
CHAPTER 4: INSTRUCTION SET
LSB
LSB
2 cycles
143