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INC [ir],n4
Function: [ir]
N's adjust ([ir] + 1)
Increments (+1) the content of the data memory addressed by the ir register (X or Y). The
operation result is adjusted with n4 as the radix.
Code:
Mnemonic
INC [%X],n4
INC [%Y],n4
Flags:
E
I
–
Src: Immediate data
Mode:
Dst: Register indirect
Extended addressing: Valid
Extended LDB
%EXT,imm8
operation: INC
[%X],n4
LDB
%EXT,imm8
INC
[%Y],n4
n4 should be specified with a value from 1 to 16.
Note:
INC [ir]+,n4
Function: [ir]
N's adjust ([ir] + 1), ir
Increments (+1) the content of the data memory addressed by the ir register (X or Y). The
operation result is adjusted with n4 as the radix. Then increments the ir register (X or Y). The
increment result of the ir register does not affect the flags.
Code:
Mnemonic
INC [%X]+,n4
INC [%Y]+,n4
Flags:
E
I
–
Src: Immediate data
Mode:
Dst: Register indirect
Extended addressing: Invalid
Note:
n4 should be specified with a value from 1 to 16.
S1C63000 CORE CPU MANUAL
Increment location [ir] in specified radix
MSB
1 1 1 0 1 1 0 0 0
1 1 1 0 1 1 0 1 0
C
Z
[00imm8]
N's adjust ([00imm8] + 1) (00imm8 = 0000H + 00H to FFH)
[FFimm8]
N's adjust ([FFimm8] + 1) (FFimm8 = FF00H + 00H to FFH)
Increment location [ir] in specified radix and increment ir reg.
ir + 1
MSB
1 1 1 0 1 1 0 0 1
1 1 1 0 1 1 0 1 1
C
Z
EPSON
CHAPTER 4: INSTRUCTION SET
LSB
[10H-n4]
1D80H–1D8FH
[10H-n4]
1DA0H–1DAFH
LSB
[10H-n4]
1D90H–1D9FH
[10H-n4]
1DB0H–1DBFH
2 cycles
2 cycles
93
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