Epson S1C63000 Core Cpu Manual page 81

Seiko epson s1c63000 cmos 4-bit single chip microcomputer core cpu manual
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AND %r,[%ir]
Function: r
r
[ir]
Performs a logical AND operation of the content of the data memory addressed by the ir
register (X or Y) and the content of the r register (A or B), and stores the result in the r register.
Code:
Mnemonic
AND %A,[%X]
AND %A,[%Y]
AND %B,[%X]
AND %B,[%Y]
Flags:
E
I
Src: Register indirect
Mode:
Dst: Register direct
Extended addressing: Valid
Extended LDB
%EXT,imm8
operation: AND %r,[%X]
LDB
%EXT,imm8
AND %r,[%Y]
AND %r,[%ir]+
Function: r
r
[ir], ir
Performs a logical AND operation of the content of the data memory addressed by the ir
register (X or Y) and the content of the r register (A or B), and stores the result in the r register.
Then increments the ir register (X or Y). The flags change due to the operation result of the r
register and the increment result of the ir register does not affect the flags.
Code:
Mnemonic
AND %A,[%X]+
AND %A,[%Y]+
AND %B,[%X]+
AND %B,[%Y]+
E
I
Flags:
Src: Register indirect
Mode:
Dst: Register direct
Extended addressing: Invalid
S1C63000 CORE CPU MANUAL
Logical AND of location [ir reg.] and r reg.
MSB
1 1 0 1 0 0 1 1 0 0 0 0 0
1 1 0 1 0 0 1 1 0 0 0 1 0
1 1 0 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 0 1 1 0 0 1 1 0
C
Z
r
r
[00imm8] (00imm8 = 0000H + 00H to FFH)
r
r
[FFimm8] (FFimm8 = FF00H + 00H to FFH)
Logical AND of location [ir reg.] and r reg. and increment ir reg.
ir + 1
MSB
1 1 0 1 0 0 1 1 0 0 0 0 1
1 1 0 1 0 0 1 1 0 0 0 1 1
1 1 0 1 0 0 1 1 0 0 1 0 1
1 1 0 1 0 0 1 1 0 0 1 1 1
C
Z
EPSON
CHAPTER 4: INSTRUCTION SET
LSB
1A60H
1A62H
1A64H
1A66H
LSB
1A61H
1A63H
1A65H
1A67H
1 cycle
1 cycle
75

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