Epson S1C63000 Core Cpu Manual page 134

Seiko epson s1c63000 cmos 4-bit single chip microcomputer core cpu manual
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CHAPTER 4: INSTRUCTION SET
SBC %B,[%ir],n4
Function: B
N's adjust (B - [ir] - C)
Subtracts the content of the data memory addressed by the ir register (X or Y) and carry (C)
from the B register. The operation result is adjusted with n4 as the radix. The C flag is set
according to the radix.
Code:
Mnemonic
SBC %B,[%X],n4
SBC %B,[%Y],n4
E
I
Flags:
Src: Register indirect
Mode:
Dst: Register direct
Extended addressing: Valid
Extended LDB
%EXT,imm8
operation: SBC
%B,[%X],n4
LDB
%EXT,imm8
SBC
%B,[%Y],n4
n4 should be specified with a value from 1 to 16. When 16 is specified for n4, the low-order 4
Note:
bits of the machine code (n3–n0) become 0000B.
SBC %B,[%ir]+,n4
Function: B
N's adjust (B - [ir] - C), ir
Subtracts the content of the data memory addressed by the ir register (X or Y) and carry (C)
from the B register. The operation result is adjusted with n4 as the radix. Then increments the ir
register (X or Y). The flags change due to the operation result of the B register and the incre-
ment result of the ir register does not affect the flags. The C flag is set according to the radix.
Code:
Mnemonic
SBC %B,[%X]+,n4 1 1 1 0 0 1 1 0 1 n3 n2 n1 n0 1CD0H–1CDFH
SBC %B,[%Y]+,n4 1 1 1 0 0 1 1 1 1 n3 n2 n1 n0 1CF0H–1CFFH
E
I
Flags:
Src: Register indirect
Mode:
Dst: Register direct
Extended addressing: Invalid
n4 should be specified with a value from 1 to 16. When 16 is specified for n4, the low-order 4
Note:
bits of the machine code (n3–n0) become 0000B.
128
Subtract with carry location [ir reg.] from B reg. in specified radix 2 cycles
MSB
1 1 1 0 0 1 1 0 0 n3 n2 n1 n0 1CC0H–1CCFH
1 1 1 0 0 1 1 1 0 n3 n2 n1 n0 1CE0H–1CEFH
C
Z
B
N's adjust (B - [00imm8] - C) (00imm8 = 0000H + 00H to FFH)
B
N's adjust (B - [FFimm8] - C) (FFimm8 = FF00H + 00H to FFH)
Subtract with carry location [ir reg.] from B reg. in specified radix and increment ir reg. 2 cycles
ir + 1
MSB
C
Z
EPSON
LSB
LSB
S1C63000 CORE CPU MANUAL

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