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CHAPTER 1: OUTLINE
1.3 Block Diagram
Figure 1.3.1 shows the S1C63000 block diagram.
QUEUE (16)
DATA ADDRESS LATCH
1.4 Input-Output Signals
Tables 1.4.1 (a) and 1.4.1 (b) show the input/output signals between the S1C63000 and peripheral circuits.
Type
Terminal name
Power supply
V
(V
DD
V
(V
SS
Clock
CLK
PK
PL
Address bus
IA00–IA15
DA00–DA15
2
BUS
TIMING & INTERRUPT
CONTROL
PC (16)
X (16)
Y (16)
SP2 (8)
SP1 (8)
Port A
16-bit ADDER
Fig. 1.3.1 S1C63000 block diagram
Table 1.4.1(a) Input/output signal list (1)
I/O
)
I
Power supply (+)
D1
Inputs a plus supply voltage.
)
I
Power supply (-)
S1
Inputs a minus supply voltage.
I
Clock input
Inputs the system clock from the peripheral circuit.
O
2-phase divided clock output
Outputs the 2-phase divided signals to be generated from the system clock
input to the CLK terminal as following phase.
O
Instruction address output
Outputs an instruction (code ROM) address.
O
Data address output
Outputs a data (RAM, I/O) address.
POWER
CONTROL
SUPPLY
A (4)
Port A
EXT (8)
ADDRESS
OPERATOR
Port B
S1C63000
Function
CLK
PK
PL
1 cycle
EPSON
IR (13)
INSTRUCTION
DECODER
Instruction
B (4)
Port B
4-bit ALU
F (4)
S1C63000 CORE CPU MANUAL
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